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US4071889A Expired / Lapsed US ⏱️ 0.0 years remaining

Central processing apparatus for generating and receiving time division multiplex signals

Assignee: Mitsubishi Electric Corp
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Filing: 1976-07-22
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Granted: 1978-01-31
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Expires: 1996-07-22
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Abstract

Abstract A central processing apparatus for use in a system which includes a plurality of remote electrical devices and a multiplex signal transmission line coupled to each of the plurality of devices. The central processing apparatus comprises an input unit coupled to the multiplex signal transmission line for receiving state signals from the plurality of devices in a time division multiplex format representing the states of the plurality of devices; an output unit coupled to the multiplex signal transmission line for transmitting logically processed signals to the plurality of devices in a time division multiplex format to control the plurality of devices; a logic processor responsive to the receiving of the state signals to generate the logically processed signals; a memory coupled to the logic processor, the input unit, and the output unit, for storing the state signals received from the plurality of devices and the logically processed signals generated by the logic processor; and a stored program control section coupled to the memory, the logic processor, the input unit, and the output unit for controlling the operation thereof.

Inventors

  • 👤 Shizuo Sumida
  • 👤 Kazuo Nii
  • 👤 Osamu Shimizu
  • 👤 Atsushi Ueda
  • 👤 Mitsuaki Ishii

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 20:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/22; G08; G08C; G08C15/00; G08C15/06; G08C15/12; B; B60; B60R; B60R16/00; B60R16/02; B60R16/03; B60R16/0315

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 188 words
In a system including a plurality of remote electrical devices, and a multiplex signal transmission line coupled to each of the plurality of devices, a central processing apparatus comprising: input means coupled to the multiplex signal transmission line for receiving state signals from the plurality of devices in a time division multiplex format representing the states of the plurality of devices; output means coupled to the multiplex signal transmission line for transmitting logically processed signals to the plurality of devices in a time division multiplex format to control the plurality of devices; logic processing means coupled to the input means and responsive to the receiving of the state signals for generating the logically processed signals; a memory coupled to the logic processing means, the input means, and the output means, for storing the state signals received from the plurality of devices and the logically processed signals generated by the logic processing means and for transferring the logically processed signals to the output means; and stored program control means coupled to the memory, the logic processing means, the input means, and the output means for controlling the operation thereof.
Claim 2
Dependent Claim 188 words
In a system including a plurality of remote electrical devices, and a multiplex signal transmission line coupled to each of the plurality of devices, a central processing apparatus comprising: input means coupled to the multiplex signal transmission line for receiving state signals from the plurality of devices in a time division multiplex format representing the states of the plurality of devices; output means coupled to the multiplex signal transmission line for transmitting logically processed signals to the plurality of devices in a time division multiplex format to control the plurality of devices; logic processing means coupled to the input means and responsive to the receiving of the state signals for generating the logically processed signals; a memory coupled to the logic processing means, the input means, and the output means, for storing the state signals received from the plurality of devices and the logically processed signals generated by the logic processing means and for transferring the logically processed signals to the output means; and stored program control means coupled to the memory, the logic processing means, the input means, and the output means for controlling the operation thereof.
Claim 3
Dependent Claim 56 words
The combination recited in claim 1 including: a synchronizing signal generator having an input and an output, the output of the generator being connected to the stored program control means, for generating synchronizing signals to synchronize the receiving of the state signals and the transmitting of the logically processed signals the in time division multiplex format.
Claim 4
Dependent Claim 29 words
The combination recited in claim 2 including: a clock signal generating circuit coupled to the input of the synchronizing signal generator for generating a clock signal of fixed frequency.

References Cited (Backward Citations)

US3413606A Cited
US3639838A Cited
US3651484A Cited
US3611311A Cited
US3697959A Cited
US3761889A Cited
US3766531A Cited
US3797901A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-01-30 1981-08-01 1982-01-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-01-30 1985-08-01 1986-01-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-01-30 1989-08-01 1990-01-31 $7700.00 Window Closed / Lapsed

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