Patent US4071822A successfully refreshed from Google Patents.
US4071822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital voltage detecting circuit for a power source
Assignee: Seiko Instruments Inc
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Filing: 1976-09-16
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Granted: 1978-01-31
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Expires: 1996-09-16
Abstract
Abstract The output voltage of a power source is converted into a time signal by a circuit comprising a capacitor to which the voltage is applied, an MOS-FET connected across the capacitor and controlling its discharge rate in accordance with the voltage of the power source and a switching circuit which controls the MOS-FET. The time period representing the voltage of the power source is displayed digitally by counting the number of standard pulses occurring during the time period and digitally displaying the pulse count.
Inventors
- 👤 Masaaki Kamiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:09
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
148 words
A voltage detecting circuit for indicating a decrease in the voltage of a power source from an initial voltage comprising means for converting the voltage of said power source into a corresponding time delay, means providing a reference time corresponding to said initial voltage, means for measuring said time delay and comparing it with said reference time and means for displaying said voltage decrease as a function of the difference between said time delay and said reference time, said converting means comprising a capacitor, means for connecting said capacitor to said power source to be charged thereby, means for discharging said capacitor at a rate dependent on the voltage of said power source, and means for detecting the discharge of said capacitor to a predetermined level, said delay time being the discharge time of said capacitor to said predetermined level after initiation of discharge by said discharging means.
Claim 2
Dependent Claim
148 words
A voltage detecting circuit for indicating a decrease in the voltage of a power source from an initial voltage comprising means for converting the voltage of said power source into a corresponding time delay, means providing a reference time corresponding to said initial voltage, means for measuring said time delay and comparing it with said reference time and means for displaying said voltage decrease as a function of the difference between said time delay and said reference time, said converting means comprising a capacitor, means for connecting said capacitor to said power source to be charged thereby, means for discharging said capacitor at a rate dependent on the voltage of said power source, and means for detecting the discharge of said capacitor to a predetermined level, said delay time being the discharge time of said capacitor to said predetermined level after initiation of discharge by said discharging means.
Claim 3
Dependent Claim
60 words
A voltage detecting circuit according to claim 1, in which said discharging means comprises an MOS-FET connected across said capacitor and a voltage divider connected across said power source and having a midpoint connected to the gate of said MOS-FET, whereby the drain current is determined by the voltage applied by said voltage divider to the gate of said MOS-FET.
Claim 4
Dependent Claim
19 words
A voltage detecting circuit according to claim 1, further comprising switching means for switching said detecting circuit ON intermittently.
Claim 5
Dependent Claim
41 words
A voltage detecting circuit according to claim 1, in which said time delay measuring means comprises a clock pulse generator and counting means for counting said clock pulse during said time delay corresponding to said voltage decrease of said power source.
Claim 6
Dependent Claim
25 words
A voltage detecting circuit according to claim 4, in which said display means comprises means for digitally displaying the counted content of said counting means.
Claim 7
Dependent Claim
132 words
A voltage detecting circuit according to claim 1, in which said time delay measuring means comprises a plurality of NOR gates each having one input terminal connected to the output of said converting means and each having another input terminal connected respectively to a delay pulse means, providing pulses of different length to said NOR gates respectively, and a like plurality of flip-flop circuits connected respectively to the outputs of said NOR gates, the delay times of said delay pulse means being progressively longer than the time delay of said converting means when said power source voltage is normal, whereby said flip-flops are successively actuated as said power source voltage decrease and said time delay becomes progressively longer so as to coincide successively with the delay times of said delay pulse means.
References Cited (Backward Citations)
US3316547A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-30 | 1981-08-01 | 1982-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-30 | 1985-08-01 | 1986-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-30 | 1989-08-01 | 1990-01-31 | $7700.00 | Window Closed / Lapsed |