Reduction of offsets in data acquisition systems

Claim 3

The method of claim 1 wherein the reference value is zero volts.

Claim 4

The method of claim 2 wherein the integrating means comprise an operational amplifier and a capacitor and the step of applying a preconditioning signal comprises integrating a pulse of current with the capacitor.

Claim 5

The method of claim 2 further comprising the step of periodically connecting feedback means to substantially cancel offset signals at the input to the integrating means.

Claim 6

The method of claim 2 wherein: a plurality of the analog-to-digital converter circuits are operated in parallel to simultaneously digitize a plurality of data signals; the preconditioning signals are applied to all of the analog-to-digital converters from a common source; and a single, common clock is utilized for timing the period in all of the analog-to-digital converters.

Claim 7

In a ramp-type, analog-to-digital converter circuit of the type comprising integrating means connected to receive and integrate signals, comparator means connected to produce a logical signal in response to the polarity of the difference of an output of the integrating means subtracted from a reference signal, and timing means functioning to produce a digitization of the time period between the start of the integration of the data signal and the occurrence of a value of the logical signal which indicates a change in the polarity of the difference; wherein the comparator means are characterized by a significant propagation delay time between the occurrence of the change of polarity of the difference and the occurrence of the corresponding value of the logical signal, the improvement comprising; means for applying a preconditioning signal to the integrating means prior to the reception of a data signal; means for causing the integrating means to integrate the preconditioning signal through a reference value until the comparator produces a signal indicating a change of polarity, whereby a negative residue signal is produced on the integrating means; means for applying the data signal to said integrating means in the presence of said residue signal; means for causing the integrating means to integrate the data and residue signals through the reference value; and means associated with said timing means for providing a digitization of the data signal without offsets attributable to propagation delays.

Claim 8

In a ramp-type, analog-to-digital converter circuit of the type comprising integrating means connected to receive and integrate signals, comparator means connected to produce a logical signal in response to the polarity of the difference of an output of the integrating means subtracted from a reference signal, and timing means functioning to produce a digitization of the time period between the start of the integration of the data signal and the occurrence of a value of the logical signal which indicates a change in the polarity of the difference; wherein the comparator means are characterized by a significant propagation delay time between the occurrence of the change of polarity of the difference and the occurrence of the corresponding value of the logical signal, the improvement comprising; means for applying a preconditioning signal to the integrating means prior to the reception of a data signal; means for causing the integrating means to integrate the preconditioning signal through a reference value until the comparator produces a signal indicating a change of polarity, whereby a negative residue signal is produced on the integrating means; means for applying the data signal to said integrating means in the presence of said residue signal; means for causing the integrating means to integrate the data and residue signals through the reference value; and means associated with said timing means for providing a digitization of the data signal without offsets attributable to propagation delays.

Claim 9

The circuit of claim 6 wherein the reference value is zero volts.

Claim 10

The method of claim 7 wherein the circuit further comprises feedback means which are periodically connected between the output of the comparator means and the input of the integrating means and which function to substantially cancel offset signals at the input of the integrating means.

Claim 11

A data acquisition system for a computerized x-ray tomography machine comprising a plurality of the circuits of claim 7 connected to simultaneously process a plurality of data signals; wherein the means for applying the preconditioning signals comprise a single pulse generator connected to supply a single preconditioning pulse to all of the converter circuits in parallel; and wherein a single, common clock supplies time base signals to the timing means in all of the converter circuits.

Claim 12

The circuit of claim 6 wherein the integrating means comprise an operational amplifier and a capacitor and, the means for applying the preconditioning signal are means for integrating a current pulse with the capacitor.