Bipolar read-only memory

Claim 2

A bipolar read-only memory containing information, comprising: input and output terminals; a matrix circuit having selection input lines, digit output lines and a plurality of Schottky barrier diodes connected between predetermined ones of said selection input lines and predetermined ones of said digit output lines in accordance with the contained information, said input and output lines being arranged in rows and columns; a selection input circuit having a first group of bipolar transistors and a first group of injection current sources one for each said first group transistor, each said first group transistor interconnecting different one of said input terminals and different one of said selection input lines; and a digit output circuit having a second group of bipolar transistors and a second group of injection current sources one for each said second group transistor, each said second group transistor interconnecting different one of said output terminals and different one of said digit output lines.

Claim 3

A bipolar read-only memory according to claim 1, in which each of said first group of transistors is an NPN transistor having its base and collector connected with its associated input terminal and selection input line respectively, the emitters of said first group of NPN transistors being connected in common to a reference potential source, each of said second group of transistors is an NPN transistor having its collector and base connected with its associated output terminal and digit output line respectively, the emitters of said second group of NPN transistors being connected in common to said reference potential source, and each of said first and second groups of injection current sources is constituted by a PNP transistor havng its collector and base connected with the base and emitter of its associated NPN transistor respectively, and its emitter connected to a positive potential source with respect to said reference potential source.

Claim 4

A bipolar read-only memory according to claim 2, in which: each of said first group of NPN transistors mainly consists of an emitter portion of a first common semiconductor region formed in a semiconductor substrate, a semiconductor base region formed in said emitter portion of said first common semiconductor region and having a conductivity type opposite to that of said first common region, and a semiconductor collector region formed in said base region and having a conductivity type opposite to that of said base region; each of said second group of NPN transistors mainly consists of an emitter portion of a second common semiconductor region formed in said semiconductor substrate, a semiconductor base region formed in said emitter portion of said second common semiconductor region and having a conductivity type opposite to that of said second common region, and a semiconductor collector region formed in said base region and having a conductivity type opposite to that of said base region; each of the PNP transistors serving as said first group of injection current sources for said first group of NPN transistors mainly consists of an emitter portion of an elongated third common semiconductor region formed in said first common semiconductor region, said emitter portion of said first common semiconductor region of its associated NPN transistor which portion also serves as the base of the PNP transistor, and said base region of said associated transistor also serving as the collector of the PNP transistor; and each of the PNP transistors serving as said second group of injection current sources for said second group of NPN transistors mainly consists of an emitter portion of an elongated fourth common semiconductor region formed in said second common semiconductor region, said emitter portion of said second common semiconductor region of its associated NPN transistor which portion also serves as the base of the PNP transistor, and said base region of said associated NPN transistor also serving as the collector of the PNP transistor.

Claim 5

A bipolar read-only memory according to claim 1, in which each of said selection input lines mainly consists of an elongated semiconductor region formed in a semiconductor substrate and each of said digit output lines mainly consists of a metal strip electrically connected with a portion of at least one of said elongated semiconductor regions to form a Schottky barrier diode at said connected portion.