Semiconductor switching and storage device

Claim 2

The bistable switch and memory cell as set forth in claim 1 wherein said field-effect transistor arrangement forms a memory cell including potential means coupled to said Schottky contact and to said at least first and second electrodes, said potential means coupled to said Schottky contact by impedance means so that the potential applied to said Schottky contact changes in dependence upon which of said either of two stable impedance states exist between said Schottky contact and one of the said at least first and second electrodes whereby the current path between said at least first and second electrodes varies in accordance with the said potential applied to said Schottky contact.

Claim 3

The bistable switch and memory cell as set forth in claim 3 including both means to apply pulses to said Schottky contact to switch said cell between said either of two stable impedance states and means to apply pulses to one of the said at least first and second electrodes such that the resultant level of current flow between said at least first and second electrodes is indicative of one or the other of the said two stable impedance states existing in said memory cell.

Claim 4

The device as set forth in claim 1 wherein said semiconductor material comprises silicon doped with a substance which creates deep energy traps.

Claim 5

The device as set forth in claim 5 wherein said silicon is doped with at least one substance of the group platinum, nickel, gold, iron, manganese, mercury, chromium, silver, copper, zinc, and cobalt.

Claim 6

The device as set forth in claim 4 wherein said metal is rhodium and said semiconductor material is gallium arsenide.

Claim 7

A field effect transistor including a source and drain electrode, the improvement comprising a gate electrode forming a Schottky barrier with the semiconductor substrate region thereof, said semiconductor substrate region including semiconductor material at least within reach of said Schottky barrier exhibiting a sufficient density of deep energy traps such that the interaction between the charge carriers thereof and said traps may assume either of two stable states to thereby provide non-volatile bistable impedance characteristics between said gate electrode and one of said source and drain electrodes.

Claim 8

A storage cell, comprising bistable field effect transistor means including a source, drain and gate electrode with said gate electrode arranged to form a Schottky contact with the semiconductor substrate of said transistor means, said semiconductor substrate exhibiting at least within the semiconductor region thereof which may be affected by potentials applied to said gate electrode, a sufficient density of deep energy traps such that the interaction between the charge carriers thereof and said traps may assume either of two stable states so as tO thereby provide a non-volatile bistable impedance characteristic between said gate electrode and one of said source and drain electrodes.

Claim 9

The storage cell as set forth in claim 9 including control means coupled to said gate electrode so that when the impedance between said gate electrode and said one of said source and drain electrodes is switched to one stable state thereof a first potential is applied to said gate electrode to provide a first impedance between said source and drain electrodes and when the impedance between said gate electrode and the said one of said source and drain electrodes is switched to the second stable state thereof a second potential is applied to said gate electrode to provide a second impedance between said source and drain electrode.

Claim 10

The storage cell as set forth in claim 10 wherein said control means includes both resistance means coupled between a source of potential and said gate electrode and pulse source means coupled to said gate electrode to control the impedance state thereof.

Claim 11

The storage cell as set forth in claim 9 wherein said gate electrode is rhodium and said semiconductor substrate is gallium arsenide.

Claim 12

The storage cell as set forth in claim 9 wherein said semiconductor substrate comprises silicon doped at least within the said semiconductor region which may be affected by potentials applied to said gate electrode, with a substance which creates said deep energy traps.

Claim 13

The storage cell as set forth in claim 13 wherein said silicon is doped at least within said region with at least one substance of the group platinum, nickel, gold, iron, manganese, mercury, chromium, silver, copper, zinc, and cobalt.

Claim 14

The storage cell as set forth in claim 11 wherein said semiconductor substrate comprises silicon doped at least within the said semiconductor region which may be affected by potentials applied to said gate electrode, with at least one substance of the group platinum, nickel, gold, iron, manganese, mercury, chromium, silver, copper, zinc, and cobalt.