Patent US2878197A successfully refreshed from Google Patents.
Patent US4069493A successfully refreshed from Google Patents.
US4069493A
Expired / Lapsed
US
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Novel integrated circuit and method of manufacturing same
Assignee: Thales SA
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Filing: 1976-04-26
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Granted: 1978-01-17
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Expires: 1996-04-26
Abstract
Abstract An integrated circuit comprises a high-resistivity substrate 1 which virtually insulates the various integrated components of the circuit from one another and reduces the parasitic capacitances. This components are constituted by ion implantation through high-precision masks, without exceeding 800° C in temperature. This is the case with the source 3, the gate 9 and the drain 4, of the field-effect transistor (shown in FIG. 1).
Inventors
- 👤 Albert Bobenrieth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10D86/00; H10D99/00; H10P; H10P30/00; H10P30/20; H10P30/22; H10W; H10W10/00; H10W10/01
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
160 words
A field effect transistor comprising: a weakly doped semiconductive substrate of a first conductivity type having a substantially plane surface, and, in said substrate, contiguous to said surface; a source and a drain region consisting of a first and a second ion implanted regions of a common depth, said common depth being on the order of one micron, said regions being highly doped by impurities of a second conductivity type opposite to said first type; a channel region consisting of a third ion implanted region of a common depth as said first and second regions and filling the whole space between said regions, said third region being of said second conductivity type but less doped than said first and second regions; a gate region consisting of a fourth ion implanted region, occupying a portion of said third region situated at equal distance of said first and second regions, said fourth region having a depth on the order of 0.5 micron.
Claim 2
Dependent Claim
160 words
A field effect transistor comprising: a weakly doped semiconductive substrate of a first conductivity type having a substantially plane surface, and, in said substrate, contiguous to said surface; a source and a drain region consisting of a first and a second ion implanted regions of a common depth, said common depth being on the order of one micron, said regions being highly doped by impurities of a second conductivity type opposite to said first type; a channel region consisting of a third ion implanted region of a common depth as said first and second regions and filling the whole space between said regions, said third region being of said second conductivity type but less doped than said first and second regions; a gate region consisting of a fourth ion implanted region, occupying a portion of said third region situated at equal distance of said first and second regions, said fourth region having a depth on the order of 0.5 micron.
Claim 3
Dependent Claim
146 words
A field effect transistor comprising: a weakly doped semiconductive substrate of a first conductivity type having a substantially plane surface, and a source and drain region contiguous to said surface, consisting of a first and a second regions of a common depth ion implanted in said substrate, said common depth being on the order of one micron, said regions being highly doped by impurities of a second conductivity type opposite to said first type; a channel region contiguous to said surface, consisting of a third region ion implanted in said substrate, of a common depth as said first and second regions and filling the whole space between said region, said third region being of said second conductivity type but less doped than said first and second regions; a Schottky gate occupying a portion of said surface situated at equal distance of said first and second regions.
Claim 4
Dependent Claim
146 words
A field effect transistor comprising: a weakly doped semiconductive substrate of a first conductivity type having a substantially plane surface, and a source and drain region contiguous to said surface, consisting of a first and a second regions of a common depth ion implanted in said substrate, said common depth being on the order of one micron, said regions being highly doped by impurities of a second conductivity type opposite to said first type; a channel region contiguous to said surface, consisting of a third region ion implanted in said substrate, of a common depth as said first and second regions and filling the whole space between said region, said third region being of said second conductivity type but less doped than said first and second regions; a Schottky gate occupying a portion of said surface situated at equal distance of said first and second regions.
Claim 5
Dependent Claim
26 words
An integrated circuit comprising a field effect transistor as claimed in claim 1, further comprising at least one resistor constituted by a portion of said substrate.
Claim 6
Dependent Claim
25 words
An integrated circuit comprising a field effect transistor as claimed in claim 2, further comprising at least one resistor constituted by a portion of substrate.
References Cited (Backward Citations)
US3413531A
Cited
US3761328A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-16 | 1981-07-18 | 1982-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-16 | 1985-07-18 | 1986-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-16 | 1989-07-18 | 1990-01-17 | $7700.00 | Window Closed / Lapsed |