US4068462A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency adjustment circuit
Assignee: Fairchild Semiconductor Corp
•
Filing: 1976-05-17
•
Granted: 1978-01-17
•
Expires: 1996-05-17
Abstract
Abstract A circuit for adjusting the frequency of operation of an electronic time keeping device, which device includes a source of clock pulses. The circuit of this invention is preferably located between the source of clock pulses and the time keeping device counting circuitry, so that the clock pulses can be periodically interrupted for a programmed amount of time. Accordingly, the variable adjustment capacitor, typically employed in prior art time keeping devices, can be eliminated.
Inventors
- 👤 Donald R. Duff
- 👤 James O. Lamb
- 👤 Donald E. Pezzolo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:53
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/022
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
162 words
A circuit for adjusting the frequency of operation of an electronic time keeping device including a source of clock pulses, said circuit comprising: a. means for storing a numeric code representative of a time delay of said clock pulses having a plurality of data output terminals; b. means for counting a time interval in proportion to said numeric code, including a plurality of data input terminals coupled to respective ones of said data output terminals of said means for storing, a plurality of data output terminals, and a clock input terminal; c. circuit means having a first input coupled to the source of clock pulses, a first clock output terminal coupled to the clock input terminal of said means for counting, a plurality of data input terminals coupled to respective ones of said data output terminals of said means for counting and a second clock output terminal disposed for supplying clock pulses of an adjusted frequency to the electronic time keeping device.
Claim 2
Dependent Claim
162 words
A circuit for adjusting the frequency of operation of an electronic time keeping device including a source of clock pulses, said circuit comprising: a. means for storing a numeric code representative of a time delay of said clock pulses having a plurality of data output terminals; b. means for counting a time interval in proportion to said numeric code, including a plurality of data input terminals coupled to respective ones of said data output terminals of said means for storing, a plurality of data output terminals, and a clock input terminal; c. circuit means having a first input coupled to the source of clock pulses, a first clock output terminal coupled to the clock input terminal of said means for counting, a plurality of data input terminals coupled to respective ones of said data output terminals of said means for counting and a second clock output terminal disposed for supplying clock pulses of an adjusted frequency to the electronic time keeping device.
Claim 3
Dependent Claim
19 words
A circuit as in claim 1 further including means for entering said numeric code into said means for storing.
Claim 4
Dependent Claim
17 words
A circuit as in claim 2 further characterized by said means for storing comprising a counter circuit.
Claim 5
Dependent Claim
48 words
A circuit as in claim 3 further characterized by said means for entering comprising a gating network responsive to a clock signal and set and display switches of the electronic time keeping device for supplying a series of pulses indicative of said numeric code to said counter circuit.
Claim 6
Dependent Claim
26 words
A circuit as in claim 1 further including means for periodically transferring said numeric code stored in said means for storing to said means for counting.
Claim 7
Dependent Claim
79 words
A circuit as in claim 5 further characterized by said means for periodically transferring comprising a gating network means having a first input terminal coupled to a clock pulse of a predetermined frequency, a plurality of said input terminals coupled to respective ones of said plurality of data output terminals of said means for storing, and having a plurality of data output terminals coupled to respective ones of said plurality of data input terminals of said means for counting.
Claim 8
Dependent Claim
161 words
A circuit as in claim 1 further characterized by said circuit means comprising: a. first gating means having a plurality of data input terminals coupled to respective ones of said data output terminals of said means for counting and having an output terminal; b. second gating means having a first input terminal coupled to the source of clock pulses, a second input terminal coupled to said output terminal of said first gating means, and an output terminal coupled to the clock input terminal of said means for counting; and, c. third gating means having a first input terminal coupled to the source of clock pulses, a second input terminal coupled to said output terminal of said first gating means, and an output terminal disposed for providing clock pulses to the time keeping device, whereby clock pulses supplied to said time keeping device are periodically interrupted for a period of time determined by said numeric code stored in said means for storing.
Claim 9
Independent Claim
84 words
A method of adjusting the frequency of operation of an electronic time keeping device, which device includes a source of clock pulses, comprising the steps of: a. inserting a numeric code into a progammable counter; b. storing the numeric code in the programmable counter; c. displaying the numeric code stored; d. transferring the numeric code to a time delay counter; and e. supplying signals from the time delay counter to a gating network to thereby interrupt the source of clock pulses at desired intervals.
Claim 10
Independent Claim
84 words
A method of adjusting the frequency of operation of an electronic time keeping device, which device includes a source of clock pulses, comprising the steps of: a. inserting a numeric code into a progammable counter; b. storing the numeric code in the programmable counter; c. displaying the numeric code stored; d. transferring the numeric code to a time delay counter; and e. supplying signals from the time delay counter to a gating network to thereby interrupt the source of clock pulses at desired intervals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-16 | 1981-07-18 | 1982-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-16 | 1985-07-18 | 1986-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-16 | 1989-07-18 | 1990-01-17 | $7700.00 | Window Closed / Lapsed |