Associative processors

Claim 1

An associative processor comprising in combination an associative store and a program store, the associative store including, an array of associative memory cells arranged in equal multi-bit memory words each cell having input, output and match paths, a plurality of response circuits one for each memory word in said array and connected to the match path of all the cells in a memory word, a multi-bit input register, for use in the content addressing operations, each bit of which is connected to the input path of the corresponding bit of all the memory words, and a multi-bit output register, for use in reading information from the store, and each bit of the output register is connected to the output path of the corresponding bit of all the memory words, the improvement comprising a command signal highway connecting the program store to all the response circuits, said highway being arranged to carry logic manipulative operation control signals, and the associative memory cells each include logic manipulative means for conditioning the cell to assume a state indicative of, i. the logic AND of an input data bit with the data bit stored in the memory cells, ii. the logic OR of an input data bit with the data bit stored in the memory cell, or iii. the inverse of the state of the data bit stored in the memory, the actual operation performed being defined by the command signals passed to the cells of a word by the activation of a response circuit following an associative store match operation.