Circuit for detecting a missed commutation in an inverter

Claim 2

A circuit for detecting a missed commutation in a self-commutating inverter including a series combination of at least first and second gate controlled rectifiers and a commutating interval current limiting center tapped reactor connected in series with and interposed between said rectifiers, and commutating means connected to the center tap of said reactor, said series combination being connected across a direct current source of potential, comprising: a. means coupled to the center tap of said reactor for generating a first signal upon detecting and for the duration of an interval when both of said rectifiers are ON; b. means, responsive to a first pulse used to initiate the interval when either of said first and second recitifiers is to be ON, for generating a second signal the duration of which is longer than the time necessary to ensure that both of said rectifiers would normally have turned ON but shorter than the final time when both of said rectifiers would still have remained ON; and c. means responsive to said first and second signals for generating a control signal to cause cessation in the operating of said inverter if said first signal fails to occur during the total occurrence of said second signal.

Claim 3

A circuit for detecting a malfunction in a self-commutating inverter according to claim 1, wherein said means for generating said first signal is comprised of: a. a voltage divider network having an output terminal at a midpoint junction of said voltage divider and a pair of external terminals connected across the direct current source of potential; b. full wave rectifier means having a pair of input and a pair of output terminals, one of said input terminals being connected to the center tap of said reactor and the other of said input terminals being connected to said output terminal of said voltage divider; c. a photodiode connected across said output terminals of said full wave rectifier means; and d. a phototransistor amplifier, optically coupled to said photodiode, having an output terminal coupled to said control signal generating means, whereby during the time when both of said gate controlled rectifiers are "ON", the potential at said output terminal of said voltage divider is equal to the potential at the center tap of said reactor, and no current flows through said photodiode, thereby resulting in the generation of said first signal at said output terminal of said phototransistor amplifier, and during the remaining time interval when only one of said first and second gate controlled rectifiers is "ON", the potential at the center tap of said reactor is unequal to the potential at said output terminal of said voltage divider, thereby causing the flow of current through said photodiode, whereupon said first signal at said output terminal of said phototransistor amplifier is extinguished.

Claim 4

A circuit for detecting a malfunction in a self-commutating inverter according to claim 1, wherein said means for generating said second signal is comprised of a one-shot multivibrator triggered by the first pulse, said mulivibrator having an output terminal.

Claim 5

A circuit for detecting a malfunction in a self-commutating inverter according to claim 3, wherein said means for generating said control signal is comprised of: a. an inverting amplifier having an input terminal, coupled to said output terminal of said one-shot multivibrator, and an output terminal; b. a flip-flop having set and reset input terminals and an output terminal, said set input terminal receiving the first pulse to set said flip-flop, and said reset input terminal being coupled to said output terminal of said phototransistor amplifier to cause said flip-flop to be reset by the leading edge of said first signal; and c. gating means having a first input terminal coupled to said output terminal of said flip-flop, a second input terminal coupled to said output terminal of said inverting amplifier, and an output terminal, whereby said control signal is generated at said output terminal of said gating means, if said flip-flop fails to be reset during the total occurrence of said second signal at said output terminal of said one-shot multivibrator.

Claim 6

A circuit for detecting a missed commutation in an inverter including a series combination of at least first and second gate controlled rectifiers, and commutating means coupled to each of said rectifiers, said series combination being connected across a direct current source of potential, comprising: a. means coupled to said inverter for generating a first signal upon detecting and for the duration of an interval when both of said rectifiers are ON; b. means, responsive to a first transition used to initiate the interval when either of said first and second rectifiers is to be ON, for generating a second signal the duration of which is longer than the time necessary to ensure that both of said rectifiers would normally have turned ON but shorter than the final time when both of said rectifiers would have remained ON; and c. means responsive to said first and second signals for generating a control signal to cause a modification in the operation of said inverter if said first signal fails to occur during the total occurrence of said second signal.

Claim 7

A circuit for detecting a missed commutation in an inverter including a series combination of at least first and second gate controlled rectifiers, and commutating means coupled to each of said rectifiers, said series combination being connected across a direct current source of potential, comprising: a. means coupled to said inverter for generating a first signal upon detecting and for the duration of an interval when both of said rectifiers are ON; b. means, responsive to a first transition used to initiate the interval when either of said first and second rectifiers is to be ON, for generating a second signal the duration of which is longer than the time necessary to ensure that both of said rectifiers would normally have turned ON but shorter than the final time when both of said rectifiers would have remained ON; and c. means responsive to said first and second signals for generating a control signal to cause a modification in the operation of said inverter if said first signal fails to occur during the total occurrence of said second signal.