Abstract A junction field effect transistor of a vertical type having: a drain region having a first conductivity type; a gate region composed of branches formed on said drain region by a selective vapor deposition or liquidous phase deposition method and having a second conductivity type opposite to the first conductivity type of the drain region, at least that surface of each of the branches of the gate region which locates on the side opposite to the drain region side being covered with an insulating layer; and source regions formed between the respective branches of the gate region by conducting a further growth of said drain region. This field effect transistor has a sufficiently reduced area of P - N junction between the gate region and the respective source regions, resulting in a marked reduction in the junction capacitance. Besides, the insulated gate region with respect to the source regions give rise to a high gate-to-source breakdown voltage property.
A junction field effect transistor of a vertical type comprising: a drain region having a first conductivity type; a gate region having a second conductivity type opposite to said first type, said gate region including spaced branches formed by a selective growth method on a top surface of the drain region to define top and side surfaces of the branches; an insulating layer covering the top surfaces and at least a portion of the side surfaces of said branches; and source regions formed by a growth of the drain region on those portions on the top surface of the drain region not covered by the spaced branches and said insulating layer.
Claim 2
Dependent Claim
111 words
A junction field effect transistor of a vertical type comprising: a drain region having a first conductivity type; a gate region having a second conductivity type opposite to said first type, said gate region including spaced branches formed by a selective growth method on a top surface of the drain region to define top and side surfaces of the branches; an insulating layer covering the top surfaces and at least a portion of the side surfaces of said branches; and source regions formed by a growth of the drain region on those portions on the top surface of the drain region not covered by the spaced branches and said insulating layer.
Claim 3
Dependent Claim
30 words
A junction field effect transistor of a vertical type according to claim 1, in which the gate region has an impurity concentration of at least 10.sup. 19 /cm 3 .
Claim 4
Dependent Claim
28 words
A junction field effect transistor of a vertical type according to claim 1, in which said insulating layer comprises a heated and oxidized portion of the gate region.
Claim 5
Dependent Claim
21 words
A junction field effect transistor of a vertical type according to claim 1, in which the insulating layer comprises silicon dioxide.
Claim 6
Dependent Claim
21 words
A junction field effect transistor of a vertical type according to claim 1, in which the insulating layer comprises silicon nitride.
Claim 7
Dependent Claim
22 words
A junction field effect transistor of a vertical type according to claim 1, in which the insulating layer comprises a metal oxide.