US4066874A
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Digital speed control system
Assignee: Motorola Solutions Inc
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Filing: 1976-07-08
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Granted: 1978-01-03
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Expires: 1996-07-08
Abstract
Abstract A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all "0"'s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register. The system also includes a second binary presettable up-counter called an Acceleration Register. The inputs of the Acceleration Register are coupled to the outputs of the Actual Count Register so that during the transfer signal the complement of the first binary number is loaded into the Acceleration Register. A decoder connected to the outputs of the Error Register interprets its contents, and a second decoder interprets the contents of the the Acceleration Register.
Inventors
- 👤 Mark Layne Shaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:57
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; G01P15/00; G01P15/16; G06; G06F; G06F7/00; G06F7/60; G06F7/62; H; H02; H02P; H02P23/00; H02P23/22
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
235 words
A digital system for use in a system for controlling vehicular speed and acceleration, said digital system comprising: counting signal means for generating a first counting signal representative of a first velocity, a second counting signal representative of a predetermined acceleration, and a third counting signal representative of a second velocity; first counting means responsive to said first, second, and third counting signals and coupled to said counting signal means for counting from an initial value to a first binary number representative of said first velocity in response to said first counting signal, counting from said first binary number to a second binary number in response to said second counting signal, and counting from an initial value to a third binary number representative of said second velocity in response to said third counting signal; second counting means coupled to said counting signal means and to said first counting means for storing the logical complement of said second binary number and counting from said complement to a fourth binary number in response to said third counting signal; first means coupled to said first counting means and said second counting means for generating said complement, and entering said complement into said second counting means; decoding means coupled to said second counting means for decoding said fourth binary number to produce a binary number representing the algebraic difference between said second binary number and said third binary number.
Claim 2
Dependent Claim
235 words
A digital system for use in a system for controlling vehicular speed and acceleration, said digital system comprising: counting signal means for generating a first counting signal representative of a first velocity, a second counting signal representative of a predetermined acceleration, and a third counting signal representative of a second velocity; first counting means responsive to said first, second, and third counting signals and coupled to said counting signal means for counting from an initial value to a first binary number representative of said first velocity in response to said first counting signal, counting from said first binary number to a second binary number in response to said second counting signal, and counting from an initial value to a third binary number representative of said second velocity in response to said third counting signal; second counting means coupled to said counting signal means and to said first counting means for storing the logical complement of said second binary number and counting from said complement to a fourth binary number in response to said third counting signal; first means coupled to said first counting means and said second counting means for generating said complement, and entering said complement into said second counting means; decoding means coupled to said second counting means for decoding said fourth binary number to produce a binary number representing the algebraic difference between said second binary number and said third binary number.
Claim 3
Dependent Claim
28 words
The digital system as recited in claim 1 further comprising second means coupled to said first counting means for resetting said first counting means to said initial value.
Claim 4
Dependent Claim
65 words
The digital system as recited in claim 1 wherein said first counting means includes a first plurality of flip-flops connected as a resettable up-counter, and said second counting means includes a second plurality of flip-flops connected as a presettable up-counter, said second counting means further including overflow means coupled to the most significant bit of said second counter means for indicating a first overflow condition.
Claim 5
Dependent Claim
102 words
The digital system as recited in claim 1 wherein said first counting means includes: a first conductor for conducting a first signal representative of said first velocity; a second conductor for conducting a second signal representative of said predetermined acceleration; an AND-type logic gate means having an output and also having one input coupled to said first conductor; an OR-type logic gate having a first input coupled to said output of said AND-type logic gate means, and also having a second input coupled to said second conductor; and said OR-type logic gate means having an output coupled to said first counting means.
Claim 6
Dependent Claim
183 words
A digital system for use in a system for controlling vehicular speed, said digital system comprising: counting signal means for generating a first counting signal representative of a first velocity, a second counting signal representative of a predetermined acceleration, and a third counting signal representative of a second velocity; first counting means responsive to said first, second, and third counting signals and coupled to said counting signal means for counting from an initial value to a first binary number representative of said first velocity in response to said first counting signal, counting from said first binary number to a second binary number in response to said second counting signal, generating the logical complement of said second binary number, and counting from said initial value to a third binary number representative of said velocity in response to said third counting signal; and second counting means coupled to said counting signal means and to said first counting means for storing said logical complement of said second binary number and counting from said complement to a fourth binary number in response to said third counting signal.
Claim 7
Dependent Claim
183 words
A digital system for use in a system for controlling vehicular speed, said digital system comprising: counting signal means for generating a first counting signal representative of a first velocity, a second counting signal representative of a predetermined acceleration, and a third counting signal representative of a second velocity; first counting means responsive to said first, second, and third counting signals and coupled to said counting signal means for counting from an initial value to a first binary number representative of said first velocity in response to said first counting signal, counting from said first binary number to a second binary number in response to said second counting signal, generating the logical complement of said second binary number, and counting from said initial value to a third binary number representative of said velocity in response to said third counting signal; and second counting means coupled to said counting signal means and to said first counting means for storing said logical complement of said second binary number and counting from said complement to a fourth binary number in response to said third counting signal.
References Cited (Backward Citations)
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Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-02 | 1981-07-04 | 1982-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-02 | 1985-07-04 | 1986-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-02 | 1989-07-04 | 1990-01-03 | $7700.00 | Window Closed / Lapsed |