Patent US4066473A successfully refreshed from Google Patents.
US4066473A
Expired / Lapsed
US
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Method of fabricating high-gain transistors
Assignee: Fairchild Semiconductor Corp
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Filing: 1976-07-15
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Granted: 1978-01-03
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Expires: 1996-07-15
Abstract
Abstract A method of fabricating bipolar transistors with increased gain. A base region is formed adjacent the collector (or emitter) region of the transistor, and a portion of the base region is then removed by etching. The emitter (or collector) is then formed by diffusing dopant into the base region where the portion has been removed, with the base region separating the emitter and collector having reduced thickness due to the etching. Advantageously, the base region may be formed with a more heavily-doped region overlying a less heavily-doped region, with a part of the more heavily-doped region removed by etching, thereby providing a highly conductive path to the lower conductivity base region separating the emitter and collector regions. The process steps are compatible with conventional integrated-circuit fabrication processes.
Inventors
- 👤 David O'Brien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:25
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10D; H10D10/00; H10D10/60; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/184; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/051; Y10S148/085; Y10S148/117; Y10S148/145; Y10S148/167; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
135 words
The method of fabricating a bipolar transistor with improved gain in a semiconductor body comprising the steps of: forming a first region of one conductivity type in said semiconductor body, forming a second region of opposite conductivity type overlying said first region and extending to a surface of said semiconductor body; removing part of said second region; and diffusing a dopant of said one conductivity type into said second region where said part has been removed, thereby converting the net conductivity of a portion of said second region to said one conductivity type, said first region of one conductivity type comprising the transistor collector, said second region of opposite conductivity type comprising the transistor base, and said portion of said second region having a net conductivity of said one conductivity type comprising the transistor emitter.
Claim 2
Independent Claim
135 words
The method of fabricating a bipolar transistor with improved gain in a semiconductor body comprising the steps of: forming a first region of one conductivity type in said semiconductor body, forming a second region of opposite conductivity type overlying said first region and extending to a surface of said semiconductor body; removing part of said second region; and diffusing a dopant of said one conductivity type into said second region where said part has been removed, thereby converting the net conductivity of a portion of said second region to said one conductivity type, said first region of one conductivity type comprising the transistor collector, said second region of opposite conductivity type comprising the transistor base, and said portion of said second region having a net conductivity of said one conductivity type comprising the transistor emitter.
Claim 3
Dependent Claim
27 words
The method of forming a transistor as defined by claim 1 wherein said one conductivity type is N type and said opposite conductivity type is P type.
Claim 4
Dependent Claim
57 words
The method of forming a transistor as defined by claim 1 wherein said second region includes a first surface-oriented portion of doped semiconductor material and a second portion of doped semiconductor material with said second portion having a dopant concentration lower than said first portion, said second portion lying between said first portion and said first region.
Claim 5
Dependent Claim
31 words
The method of forming a transistor as defined by claim 1 wherein said first region comprises a buried layer in a semiconductor wafer and an overlying epitaxial layer on said wafer.
Claim 6
Dependent Claim
25 words
The method of forming a transistor as defined by claim 4 wherein said second region comprises a diffused surface-oriented portion and an ion-implanted second portion.
Claim 7
Dependent Claim
23 words
The method of forming a transistor as defined by claim 5 wherein said part of said first region is removed by chemical etching.
Claim 8
Independent Claim
154 words
The method of forming a bipolar transistor in a semiconductor body comprising the steps of: forming a first region of one conductivity type in said semiconductor body, said first region including a buried layer in said semiconductor body and an epitaxial layer overlying said buried layer; forming a second region of opposite type conductivity over-lying said first region and extending to a surface of said semiconductor body, said second region including a first surface-oriented portion of doped semiconductor material and a second portion of doped semiconductor material of lower dopant concentration than said first portion, said second portion lying between said first portion and said first region; removing at least part of said first portion of said second region; and diffusing a dopant of said one conductivity type into said second region where said part has been removed, thereby converting the net conductivity of some of said second region to said one conductivity type.
Claim 9
Independent Claim
154 words
The method of forming a bipolar transistor in a semiconductor body comprising the steps of: forming a first region of one conductivity type in said semiconductor body, said first region including a buried layer in said semiconductor body and an epitaxial layer overlying said buried layer; forming a second region of opposite type conductivity over-lying said first region and extending to a surface of said semiconductor body, said second region including a first surface-oriented portion of doped semiconductor material and a second portion of doped semiconductor material of lower dopant concentration than said first portion, said second portion lying between said first portion and said first region; removing at least part of said first portion of said second region; and diffusing a dopant of said one conductivity type into said second region where said part has been removed, thereby converting the net conductivity of some of said second region to said one conductivity type.
Claim 10
Dependent Claim
39 words
The method of forming a transistor as defined by claim 7 and further including after removing at least part of said second portion the step of heating said semiconductor body to modify the impurity distribution of said base region.
Claim 11
Dependent Claim
77 words
In the fabrication of bipolar transistors having emitter and collector regions of one conductivity type separated by a base region of opposite conductivity type, the method of increasing transistor gain by reducing base region conductivity and thickness, comprising the steps of forming a surface-oriented base region of said opposite conductivity type in said collector region of a semiconductor body, and removing a portion of said base region by etching, thereby reducing the thickness of said base region.
Claim 12
Dependent Claim
77 words
In the fabrication of bipolar transistors having emitter and collector regions of one conductivity type separated by a base region of opposite conductivity type, the method of increasing transistor gain by reducing base region conductivity and thickness, comprising the steps of forming a surface-oriented base region of said opposite conductivity type in said collector region of a semiconductor body, and removing a portion of said base region by etching, thereby reducing the thickness of said base region.
Claim 13
Dependent Claim
48 words
The method defined by claim 9 wherein said base region includes a first surface-oriented portion of doped semiconductor material and a second portion of doped semiconductor material lying between said first portion and said collector region, said second portion having a lower dopant concentration than said first portion.
Claim 14
Dependent Claim
30 words
The method as defined by claim 10 wherein said second region comprises a diffused surface-oriented portion and an ion-implanted second portion lying between said first portion and said collector region.
Claim 15
Dependent Claim
27 words
The method as defined by claim 11 wherein said collector region comprises a buried layer in a semiconductor wafer and an overlying epitaxial layer on said wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-02 | 1981-07-04 | 1982-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-02 | 1985-07-04 | 1986-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-02 | 1989-07-04 | 1990-01-03 | $7700.00 | Window Closed / Lapsed |