Patent US4064526A successfully refreshed from Google Patents.
US4064526A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I.I.L. with graded base inversely operated transistor
Assignee: Toshiba Corp
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Filing: 1975-12-24
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Granted: 1977-12-20
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Expires: 1995-12-24
Abstract
Abstract An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate. An integrated injection logic circuit is comprised of a lateral NPN transistor whose emitter, base and collector are constituted by said first P type region, first N type region and P type semiconductor layer, respectively, and a vertical PNP transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, P type semiconductor layer plus second P type region, and second N type region, respectively.
Inventors
- 👤 Yukuya Tokumaru
- 👤 Masanori Nakai
- 👤 Satoshi Shinozaki
- 👤 Junichi Nakamura
- 👤 Shintaro Ito
- 👤 Yoshio Nishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/652; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/087; Y10S148/167
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
239 words
An integrated injection logic semiconductor device comprising a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type laminated on said one conductivity type semiconductor substrate and having a lower impurity concentration than said semiconductor substrate, a first one conductivity type region formed in a manner penetrating through said opposite conductivity type semiconductor layer to reach said one conductivity type semiconductor substrate, a first opposite conductivity type region formed in said first one conductivity type region, at least one second one conductivity type region formed in said opposite conductivity type layer, and a second opposite conductivity type region formed beneath said second one conductivity type region only and connected to said one conductivity type semiconductor substrate, said second opposite conductivity type region having an impurity concentration sharply declining adjacent said substrate and decreasing toward said second one conductivity type region, the peak value of said impurity concentration being higher than that of the semiconductor layer of opposite conductivity type and lower than that of the substrate, whereby a lateral transistor is constituted by said first opposite conductivity type region, said frist one conductivity type region, and said opposite conductivity type semiconductor layer and a vertical transistor is constituted by said one conductivity type semiconductor substrate, said opposite conductivity type semiconductor layer plus said second opposite conductivity type region for providing an accelerating electric field to improve transport efficiency, and said second one conductivity type region.
Claim 2
Dependent Claim
239 words
An integrated injection logic semiconductor device comprising a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type laminated on said one conductivity type semiconductor substrate and having a lower impurity concentration than said semiconductor substrate, a first one conductivity type region formed in a manner penetrating through said opposite conductivity type semiconductor layer to reach said one conductivity type semiconductor substrate, a first opposite conductivity type region formed in said first one conductivity type region, at least one second one conductivity type region formed in said opposite conductivity type layer, and a second opposite conductivity type region formed beneath said second one conductivity type region only and connected to said one conductivity type semiconductor substrate, said second opposite conductivity type region having an impurity concentration sharply declining adjacent said substrate and decreasing toward said second one conductivity type region, the peak value of said impurity concentration being higher than that of the semiconductor layer of opposite conductivity type and lower than that of the substrate, whereby a lateral transistor is constituted by said first opposite conductivity type region, said frist one conductivity type region, and said opposite conductivity type semiconductor layer and a vertical transistor is constituted by said one conductivity type semiconductor substrate, said opposite conductivity type semiconductor layer plus said second opposite conductivity type region for providing an accelerating electric field to improve transport efficiency, and said second one conductivity type region.
Claim 3
Dependent Claim
29 words
An integrated injection logic semiconductor device according to claim 1, wherein an ohmic contact region of said opposite conductivity type is formed in said opposite conductivity type semiconductor layer.
Claim 4
Dependent Claim
272 words
An integrated injection logic semiconductor device comprising a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type laminated on said one conductivity type semiconductor substrate, and having a lower impurity concentration than said semiconductor substrate, a first one conductivity type region formed in the form of a grid in a manner penetrating through said opposite conductivity type semiconductor layer to reach said one conductivity type semiconductor substrate, a first opposite conductivity type region formed in the form of a grid in said grid shape first one conductivity type region, a second one conductivity type region formed in each of plural opposite conductivity type semiconductor sections formed by dividing said opposite conductivity type semiconductor layer by said grid shape first one conductivity type region, and a second opposite conductivity type region formed beneath said second one conductivity type region only in a manner connected directly to said semiconductor substrate, said second opposite conductivity type region having an impurity concentration sharply declining adjacent said substrate and decreasing toward said second one conductivity type region, the peak value of said impurity concentration being higher than that of the semiconductor layer of opposite conductivity type and lower than that of the substrate, whereby a lateral transistor is constituted by said first opposite conductivity type region, said first one conductivity type region, and said opposite conductivity type semiconductor layer and a vertical transistor is constituted by said one conductivity type semiconductor substrate, said opposite conductivity type semiconductor layer plus said second opposite conductivity type region and for providing an accelerating field to improve transport efficiency, and said second one conductivity type region.
Claim 5
Dependent Claim
272 words
An integrated injection logic semiconductor device comprising a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type laminated on said one conductivity type semiconductor substrate, and having a lower impurity concentration than said semiconductor substrate, a first one conductivity type region formed in the form of a grid in a manner penetrating through said opposite conductivity type semiconductor layer to reach said one conductivity type semiconductor substrate, a first opposite conductivity type region formed in the form of a grid in said grid shape first one conductivity type region, a second one conductivity type region formed in each of plural opposite conductivity type semiconductor sections formed by dividing said opposite conductivity type semiconductor layer by said grid shape first one conductivity type region, and a second opposite conductivity type region formed beneath said second one conductivity type region only in a manner connected directly to said semiconductor substrate, said second opposite conductivity type region having an impurity concentration sharply declining adjacent said substrate and decreasing toward said second one conductivity type region, the peak value of said impurity concentration being higher than that of the semiconductor layer of opposite conductivity type and lower than that of the substrate, whereby a lateral transistor is constituted by said first opposite conductivity type region, said first one conductivity type region, and said opposite conductivity type semiconductor layer and a vertical transistor is constituted by said one conductivity type semiconductor substrate, said opposite conductivity type semiconductor layer plus said second opposite conductivity type region and for providing an accelerating field to improve transport efficiency, and said second one conductivity type region.
Claim 6
Dependent Claim
27 words
An integrated injection logic semiconductor device according to claim 3, wherein an ohmic contact region is formed in each of said plural opposite conductivity type semiconductor sections.
Claim 7
Dependent Claim
243 words
An integrated injection logic semiconductor device comprising an N type semiconductor substrate, a P type semiconductor layer laminated on said N type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a first N type region formed in the form of a grid in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in the form of a grid in said grid shape first N type region, a second N type region formed in each of plural P type semiconductor sections formed by dividing said P type semiconductor layer by said grid shape first N type region, and a second P type region formed beneath said second N type region only and connected directly to said semiconductor substrate, said second P type region having an impurity concentration sharply declining adjacent said substrate and decreasing toward said second N type region, the peak value of said impurity concentration being higher than that of the N type semiconductor layer and lower than that of the substrate, whereby a lateral PNP transistor is constituted by said first P type region, said first N type region, and said P type semiconductor layer and a vertical NPN transistor is constituted by said N type semiconductor substrate, said P type semiconductor layer plus said second P type region for providing an accelerating field to improve transport efficiency, and said second N type region.
Claim 8
Dependent Claim
243 words
An integrated injection logic semiconductor device comprising an N type semiconductor substrate, a P type semiconductor layer laminated on said N type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a first N type region formed in the form of a grid in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in the form of a grid in said grid shape first N type region, a second N type region formed in each of plural P type semiconductor sections formed by dividing said P type semiconductor layer by said grid shape first N type region, and a second P type region formed beneath said second N type region only and connected directly to said semiconductor substrate, said second P type region having an impurity concentration sharply declining adjacent said substrate and decreasing toward said second N type region, the peak value of said impurity concentration being higher than that of the N type semiconductor layer and lower than that of the substrate, whereby a lateral PNP transistor is constituted by said first P type region, said first N type region, and said P type semiconductor layer and a vertical NPN transistor is constituted by said N type semiconductor substrate, said P type semiconductor layer plus said second P type region for providing an accelerating field to improve transport efficiency, and said second N type region.
Claim 9
Dependent Claim
26 words
An integrated injection logic semiconductor device according to claim 5, wherein an ohmic contact region is formed in each of said plural P type semiconductor sections.
Claim 10
Dependent Claim
27 words
An integrated injection logic semiconductor device according to claim 5, wherein said first N type region has a higher impurity concentration than said P type semiconductor layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-19 | 1981-06-20 | 1981-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-19 | 1985-06-20 | 1985-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-19 | 1989-06-20 | 1989-12-20 | $7700.00 | Window Closed / Lapsed |