Patent US4063291A successfully refreshed from Google Patents.
US4063291A
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Apparatus and method for encoding and decoding digital information
Assignee: United States Department of the Navy
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Filing: 1976-10-15
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Granted: 1977-12-13
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Expires: 1996-10-15
Abstract
Abstract An encoding system wherein digital information comprising data, clock, andartitioning components is coupled to an encoding means comprising interconnected digital elements to generate a serial encoded signal having the encoded data, clock, and partitioning components inherent in the structure of the encoded signal. The encoded signal may be stored in a magnetic record/reproduce system and subsequently coupled to a decoding means comprising interconnected digital elements to recover the data, clock, and partitioning components of the original digital information.
Inventors
- 👤 Edward W. Gennetten
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:13
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G11B20/12
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
220 words
An apparatus for encoding and decoding digital information comprising data, clock and partitioning components, said apparatus comprising: encoding means for receiving said digital information and for encoding said data, clock and partitioning components in an encoded signal comprised of a serial stream of coded bit periods wherein each of said encoded components is inherent in the structure of said encoded signal, wherein said data component comprises discrete sets of sequential data bit periods, wherein each uncoded logic 1 data bit of said sequence is defined in said encoded signal by a transition to a predetermined logic level in one of said coded bit periods and each uncoded logic 0 data bit of said sequence is defined in said encoded signal by a transition of the other logic level in one of said coded bit periods, and wherein said partitioning component of said digital information is defined in said encoded signal by a blank interval occurring during a selected number of adjacent coded bit periods during which blank interval no transitions to a predetermined logic level occur; and said apparatus further comprising decoding means coupled to said encoding means for receiving said encoded signal and responding thereto by generating a first output comprising said data component, a second output comprising said clock component, and a third output comprising said partitioning component.
Claim 2
Independent Claim
220 words
An apparatus for encoding and decoding digital information comprising data, clock and partitioning components, said apparatus comprising: encoding means for receiving said digital information and for encoding said data, clock and partitioning components in an encoded signal comprised of a serial stream of coded bit periods wherein each of said encoded components is inherent in the structure of said encoded signal, wherein said data component comprises discrete sets of sequential data bit periods, wherein each uncoded logic 1 data bit of said sequence is defined in said encoded signal by a transition to a predetermined logic level in one of said coded bit periods and each uncoded logic 0 data bit of said sequence is defined in said encoded signal by a transition of the other logic level in one of said coded bit periods, and wherein said partitioning component of said digital information is defined in said encoded signal by a blank interval occurring during a selected number of adjacent coded bit periods during which blank interval no transitions to a predetermined logic level occur; and said apparatus further comprising decoding means coupled to said encoding means for receiving said encoded signal and responding thereto by generating a first output comprising said data component, a second output comprising said clock component, and a third output comprising said partitioning component.
Claim 3
Dependent Claim
64 words
The apparatus of claim 1 wherein said encoding means comprises: an exclusive OR gate having first and second inputs for receiving respectively, said data and clock components; partition pulse means for providing an output that is derived from said partition component; and an AND gate having inputs operably coupled to the respective outputs of said exclusive OR gate and to said partition pulse means.
Claim 4
Dependent Claim
23 words
The apparatus of claim 1 wherein said encoding means and said decoding means are coupled together by means of a serial channel means.
Claim 5
Dependent Claim
19 words
The apparatus of claim 3 wherein said encoding means and said decoding means each comprise selected interconnected digital elements.
Claim 6
Dependent Claim
24 words
The apparatus of claim 4 wherein said encoding means comprises two interconnected logic gates coupled to said serial channel means through a deslivering means.
Claim 7
Dependent Claim
83 words
The apparatus of claim 4 wherein the digital elements comprising said decoding means include: a first non-retriggerable monostable operably coupled to a source of said encoded signal; a second non-triggerable monostable operably coupled to a source of the complement of said encoded signal; a NOR gate operably coupled to outputs of said first and second non-retriggerable monostables; an edge triggered flip-flop operably coupled to the output of said NOR gate; and a retriggerable monostable operably coupled to the output of said NOR gate.
Claim 8
Dependent Claim
14 words
The apparatus of claim 6 wherein said serial channel means comprises a record/reproduce system.
Claim 9
Dependent Claim
26 words
The apparatus of claim 1 wherein each of said data-defining transitions in said encoded signal occurs in the middle of one of said coded bit periods.
Claim 10
Dependent Claim
39 words
The apparatus of claim 1 wherein each of said blank intervals is followed in said encoded signal by a synchronizing interval comprising a selected number of adjacent coded bit periods in which transitions to a predetermined logic level occur.
Claim 11
Dependent Claim
28 words
The apparatus of claim 9 wherein each of said blank intervals and each of said synchronizing intervals comprises one of said coded bit periods of said encoded signal.
Claim 12
Dependent Claim
115 words
In an apparatus including first means for generating a Manchester-type code characterized by a self clocking encoded signal having data and clock components on the same waveform, wherein said data component comprises discrete sets of sequential data bit periods, wherein each logic 1 and logic 0 of said data is recognizable on said waveform as either a negative or a positive transition in one of said bit periods, the improvement comprising: second means operably coupled to said first means for generating a partition signal inherent on said waveform and recognizable as a blank interval occurring during at least one of said bit periods during which blank interval no transitions to a predetermined logic level occur.
Claim 13
Dependent Claim
115 words
In an apparatus including first means for generating a Manchester-type code characterized by a self clocking encoded signal having data and clock components on the same waveform, wherein said data component comprises discrete sets of sequential data bit periods, wherein each logic 1 and logic 0 of said data is recognizable on said waveform as either a negative or a positive transition in one of said bit periods, the improvement comprising: second means operably coupled to said first means for generating a partition signal inherent on said waveform and recognizable as a blank interval occurring during at least one of said bit periods during which blank interval no transitions to a predetermined logic level occur.
Claim 14
Dependent Claim
53 words
The apparatus of claim 11 wherein the improvement further comprises: said second means being interconnected with said first means such that in said encoded signal, each of said blank intervals is followed by a synchronizing interval comprising at least one coded bit period in which a transition to a predetermined logic level occurs.
Claim 15
Dependent Claim
49 words
The apparatus of claim 11 further including: decoding means operably coupled to said first and second means for receiving said encoded signal and responding thereto by generating a first output comprising said data component, a second output comprising said clock component and a third output comprising said partition signal.
Claim 16
Independent Claim
184 words
A method for encoding and decoding digital information comprising data, clock, and partitioning components, said method comprising the steps of: a. encoding said data, clock, and partitioning components of said digital information in an encoded signal wherein each of said encoded components is inherent in the structure of said encoded signal, wherein said data component comprises discrete sets of sequential data bit periods, wherein each uncoded logic 1 data bit of said sequence is defined in said encoded signal by a transition to a predetermined logic level in one of said coded bit periods and each uncoded logic 0 data bit of said sequence is defined in said encoded signal by a transition to the other logic level in one of said coded bit periods, and wherein said partitioning component of said digital-information is defined in said encoded signal by a blank interval occurring during at least one coded bit period during which blank interval no transitions to a predetermined logic level occur; b. decoding said encoded signal to recover said data component, said clock component and said partitioning component of said digital information.
Claim 17
Independent Claim
184 words
A method for encoding and decoding digital information comprising data, clock, and partitioning components, said method comprising the steps of: a. encoding said data, clock, and partitioning components of said digital information in an encoded signal wherein each of said encoded components is inherent in the structure of said encoded signal, wherein said data component comprises discrete sets of sequential data bit periods, wherein each uncoded logic 1 data bit of said sequence is defined in said encoded signal by a transition to a predetermined logic level in one of said coded bit periods and each uncoded logic 0 data bit of said sequence is defined in said encoded signal by a transition to the other logic level in one of said coded bit periods, and wherein said partitioning component of said digital-information is defined in said encoded signal by a blank interval occurring during at least one coded bit period during which blank interval no transitions to a predetermined logic level occur; b. decoding said encoded signal to recover said data component, said clock component and said partitioning component of said digital information.
Claim 18
Dependent Claim
17 words
The method of claim 14 wherein said encoded signal comprises a serial stream of coded bit periods.
Claim 19
Dependent Claim
37 words
The method of claim 14 wherein each of said blank intervals of said encoded signal is followed by a synchronizing interval comprising at least one coded bit period in which transitions to a predetermined logic level occur.
Claim 20
Dependent Claim
24 words
The method of claim 16 wherein said step of encoding and said step of decoding are accomplished by means of selected interconnected digital elements.
Claim 21
Dependent Claim
26 words
The method of claim 17 wherein said encoded signal is stored on a magnetic medium after said step of encoding and before said step of decoding.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-12 | 1981-06-13 | 1981-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-12 | 1985-06-13 | 1985-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-12 | 1989-06-13 | 1989-12-13 | $7700.00 | Window Closed / Lapsed |