Channel selection apparatus provided with memory for digitalizing and storing channel selection voltage

Claim 1

A channel selection apparatus comprising; an electronic tuner using a voltage-dependent variable reactance element as a turning element, a memory block having a plurality of memory addresses which are addressed in the matrix state by an X-address and a Y-address, said memory block storing digital voltage signals at said memory addresses which are digital versions of a plurality of channel selection voltages to be applied to said voltage-dependent reactance element for selecting a plurality of channels, said memory block further storing skip control signals for controlling whether the channels corresponding to the respective memory addresses are to be selected or to be skipped, an addressing circuit for specifying an address to be read out of said memory block comprising an X-addressing counter for addressing an X-address of said memory block and a Y-addressing counter for addressing a Y-address of said memory block, said Y-addressing counter being controlled by the final bit output of said X-addressing counter, a switch, a monostable multivibrator for generating a pulse signal when said switch is operated, said multivibrator supplying a pulse signal to said X-addressing counter for shifting the read-out address by one address, a skipping pulse generating circuit connected to the output of said memory block for activating said addressing circuit to step the readout address by one when said skip control signal read out of said memory block at the address specified by said addressing circuit indicates that a skipping pulse is to be supplied to said X-addressing counter, and a digital to analog converter for converting the digital voltage signals read out of said memory block at the address specified by said addressing circuit to an analog channel selection voltage for application to the voltage-dependent variable reactance element of said electronic tuner.