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US4060828A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having multi-layer wiring structure with additional through-hole interconnection
Assignee: Hitachi Ltd
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Filing: 1976-08-03
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Granted: 1977-11-29
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Expires: 1996-08-03
Abstract
Abstract A semiconductor device has a through-hole cut in the insulating layer beneath the bonding pad of the wiring layer having a bonding pad onto which a metal wiring is to be connected and this wiring layer is connected through the through-hole with the lower wiring layer so that the connection between the wiring layer having a bonding pad and the lower wiring layer rarely corrodes or becomes disconnected.
Inventors
- 👤 Koichiro Satonaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10P; H10P14/00; H10P14/60; H10P14/68; H10P14/683; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W72/50; H10W72/531; H10W72/536; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/931; H10W72/932; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
118 words
A semiconductor device having a multi-layer wiring structure, comprising: a. a first wiring layer formed on one main surface of a semiconductor substrate; b. a first insulating layer formed on said first wiring layer; c. a second wiring layer formed on said first insulating layer; d. metal leads bonded to predetermined portions of said second wiring layer; and e. a second insulating layer formed on the entire surface of said second wiring layer except said predetermined portions of said second wiring layer, said first wiring layer being electrically connected with said second wiring layer through first through-holes cut in those portions of said first insulating layer which are just beneath said predetermined portions of said second wiring layer.
Claim 2
Dependent Claim
118 words
A semiconductor device having a multi-layer wiring structure, comprising: a. a first wiring layer formed on one main surface of a semiconductor substrate; b. a first insulating layer formed on said first wiring layer; c. a second wiring layer formed on said first insulating layer; d. metal leads bonded to predetermined portions of said second wiring layer; and e. a second insulating layer formed on the entire surface of said second wiring layer except said predetermined portions of said second wiring layer, said first wiring layer being electrically connected with said second wiring layer through first through-holes cut in those portions of said first insulating layer which are just beneath said predetermined portions of said second wiring layer.
Claim 3
Dependent Claim
49 words
A semiconductor device as claimed in claim 1, wherein said first wiring layer is electrically connected with said second wiring layer except said predetermined portions through second through-holes cut in those portions of said first insulating layer which are different from the portions where said first through-holes are formed.
Claim 4
Dependent Claim
177 words
A semiconductor device having comprising: a. a semiconductor substrate in which desired circuit elements are formed; b. a first insulating layer formed on said semiconductor substrate; c. at least one wiring layer of the first level formed on said first insulating layer and connected with said circuit elements through the first through-hole cut in said first insulating layer; d. a second insulating layer formed on said wiring layer of the first level; e. at least one wiring layer of the second level having a bonding pad formed on said second insulating layer; f. a metal wire connected with bonding pad of said wiring layer of the second level; and g. a third insulating layer formed on the entire surface of said wiring layer of the second level except said bonding pad, wherein said wiring layer of the first level is electrically connected with said wiring layer of the second level through second through-hole cut in those portions of said second insulating layer which are just beneath said bonding pad of said wiring layer of the second level.
Claim 5
Dependent Claim
177 words
A semiconductor device having comprising: a. a semiconductor substrate in which desired circuit elements are formed; b. a first insulating layer formed on said semiconductor substrate; c. at least one wiring layer of the first level formed on said first insulating layer and connected with said circuit elements through the first through-hole cut in said first insulating layer; d. a second insulating layer formed on said wiring layer of the first level; e. at least one wiring layer of the second level having a bonding pad formed on said second insulating layer; f. a metal wire connected with bonding pad of said wiring layer of the second level; and g. a third insulating layer formed on the entire surface of said wiring layer of the second level except said bonding pad, wherein said wiring layer of the first level is electrically connected with said wiring layer of the second level through second through-hole cut in those portions of said second insulating layer which are just beneath said bonding pad of said wiring layer of the second level.
Claim 6
Dependent Claim
156 words
A semiconductor device as claimed in claim 3, wherein: a. said wiring layer of the second level having the bonding pad is connected with said wiring layer of the first level through another wiring layer of the first level formed on the first insulating layer and another wiring layer of the second level formed on the second insulating layer; b. said wiring layer of the second level having the bonding pad is connected with said another wiring layer of the first level through the second through-hole formed in said second insulating layer immediately beneath the bonding pad; c. said anothr wiring layer of the first level is connected with said another wiring layer of the second level through a third through-hole formed in the second insulating layer; and d. said another wiring layer of the second level is connected with said wiring layer of the first level through a fourth through-hole formed in the second layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-28 | 1981-05-30 | 1981-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-28 | 1985-05-30 | 1985-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-28 | 1989-05-30 | 1989-11-29 | $7700.00 | Window Closed / Lapsed |