Linearized bridge circuitry

Claim 2

In a linearized bridge circuit of the type wherein a sensor presenting a resistance related to a parameter by a second order polynomial is disposed in the unknown leg and a voltage divider is disposed in the balance leg, the improvement comprising: circuit means for continuously balancing the bridge circuit with feedback from across the conventional null measurement terminals thereof to a voltage divided point in the balance leg thereof, the voltage at said point divided by the current level of said feedback having substantially a linear relationship to the parameter of the sensor.

Claim 3

The combination of claim 1 wherein said circuit means includes an operational amplifier with the differential inputs thereof connected across the null measurement terminals and a fixed resistor interconnecting output therefrom to the voltage divided point, a ratio determined by the voltage levels at both terminals of said fixed resistor having substantially a linear relationship to the parameter of the sensor.

Claim 4

The combination of claim 2 wherein the sensor is a platinum element which presents a resistance relating to the temperature thereof.

Claim 5

The combination of claim 2 and further including a circuit means for continuously monitoring said ratio determined by the voltage levels in recurring cycles.

Claim 6

The combination of claim 4 wherein said continuously monitoring circuit means includes: means for integrating the output from said operational amplifier relative to the voltage division level in the balance leg; means for multiplying the voltage division level in the balance leg by a constant; means for differentially comparing the outputs from said integrating means and said multiplying means; a counter; and a logic means connected to said integrating means and said comparator means for enabling said counter during the interval required for output from said integrating means to reach the output level from said multiplying means in continuously recurring cycles.

Claim 7

The combination of claim 5 wherein said logic means includes: an AND gate having one input thereof connected to the output from said comparator means; reset means for starting said integrating means; and clock means for generating continuous pulses having the frequency of the recurring cycles, output from said clock means being connected to control said reset means and to the other input of said AND gate.

Claim 8

The combination of claim 6 wherein said reset means is an FET switch.

Claim 9

The combination of claim 5 wherein said integrating means includes a second operational amplifier having the noninverting input thereof connected to the voltage divided level in the balance leg while the inverting input thereof is connected to a feedback capacitor and to output from said first operational amplifier in the bridge circuit through a fixed resistor; wherein said multiplying means includes a third operational amplifier having the noninverting input thereof connected to the voltage divided level in the balance leg while inverting input is connected to a feedback resistor and to ground through a fixed resistor; wherein said comparator means includes a fourth operational amplifier having the inverting input thereof connected to output from said second operational amplifier and the noninverting input thereof connected to output from said third operational amplifier; and wherein said logic means includes an AND gate having one input thereof connected to output from said fourth operational amplifier, an FET swtich shunt connected across said feedback capacitor of said second operational amplifier, and clock means for generating continuous pulses having the frequency of the recurring cycles, output from said clock means being connected to the other input of said AND gate and to control said FET switch.

Claim 10

The combination of claim 8 wherein the sensor is a platinum element which presents a resistance relating to the temperature thereof.