Patent US4059808A successfully refreshed from Google Patents.
US4059808A
Expired / Lapsed
US
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Differential amplifier
Assignee: Hitachi Ltd
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Filing: 1976-07-23
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Granted: 1977-11-22
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Expires: 1996-07-23
Abstract
Abstract In a semiconductor differential amplifier comprising a differential pair of npn transistors having the emitters connected to the emitter of lateral transistors, the bases supplied with an input signal, and the collectors connected in common to one terminal of the voltage source so as to derive the output signal from the collector of the lateral transistor, the emitter voltage of each of the differential pair transistors is applied to the common base of the pnp lateral transistors through a constant voltage element consisting of a transistor or a diode. Therefore, the voltage applied between the base and the substrate of the lateral transistor is reduced and hence the tolerance to the reverse breakdown voltage is increased and simplification of the circuit structure becomes possible. Further, a sink current path is provided between the base of the pnp lateral transistor and the other terminal of the voltage source to allow a stabilized bias current to flow through the differential amplifier.
Inventors
- 👤 Yoshio Sakamoto
- 👤 Masahiro Yamamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:17
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/30; H03F3/3069; H03F3/3071; H03F2203/00; H03F2203/45; H03F2203/45094
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
189 words
A differential amplifier comprising: an input amplifier stage comprising a first pair of npn transistors having collector electrodes connected to a first voltage supply, base electrodes forming input terminals of said differential amplifier and emitter electrodes, and a second pair of pnp transistors each having an emitter electrode connected to the emitter electrode of a corresponding one of said first pair of npn transistors, a base electrode and a collector electrode; a third pair of pnp transistors each having a base electrode connected to its collector electrode and having substantially the same operating characteristics as those of said second pair of pnp transistors, each transistor of said third pair of pnp transistors having an emitter electrode connected to the emitter of a corresponding one of said second pair of pnp transistors, each transistor of said third pair of pnp transistors having a base electrode connected to the base electrode of the corresponding one of said second pair of pnp transistors, thereby providing bias currents through said second pair of pnp transistors and compensating for changes in operating characteristics of said second pair of pnp transistors due to temperature fluctuations;
Claim 2
Dependent Claim
189 words
A differential amplifier comprising: an input amplifier stage comprising a first pair of npn transistors having collector electrodes connected to a first voltage supply, base electrodes forming input terminals of said differential amplifier and emitter electrodes, and a second pair of pnp transistors each having an emitter electrode connected to the emitter electrode of a corresponding one of said first pair of npn transistors, a base electrode and a collector electrode; a third pair of pnp transistors each having a base electrode connected to its collector electrode and having substantially the same operating characteristics as those of said second pair of pnp transistors, each transistor of said third pair of pnp transistors having an emitter electrode connected to the emitter of a corresponding one of said second pair of pnp transistors, each transistor of said third pair of pnp transistors having a base electrode connected to the base electrode of the corresponding one of said second pair of pnp transistors, thereby providing bias currents through said second pair of pnp transistors and compensating for changes in operating characteristics of said second pair of pnp transistors due to temperature fluctuations;
Claim 3
Dependent Claim
98 words
bias circuit means connected to the base electrodes of said third pair of pnp transistors for supplying bias currents therein; load circuit means connected to the collector electrodes of said second pair of pnp transistors for providing at one of the collector electrodes of said second pair of pnp transistors, differential voltage changes having a correspondence to the variations between input signals applied to said input terminals; and output means connected to the collector electrode of one of said second pair of pnp transistors for deriving said differential voltage changes as an output signal of said differential amplifier.
Claim 4
Dependent Claim
98 words
bias circuit means connected to the base electrodes of said third pair of pnp transistors for supplying bias currents therein; load circuit means connected to the collector electrodes of said second pair of pnp transistors for providing at one of the collector electrodes of said second pair of pnp transistors, differential voltage changes having a correspondence to the variations between input signals applied to said input terminals; and output means connected to the collector electrode of one of said second pair of pnp transistors for deriving said differential voltage changes as an output signal of said differential amplifier.
Claim 5
Dependent Claim
107 words
The differential amplifier according to claim 1, in which said load circuit means comprises a fourth pair of npn transistors having commonly connected base electrodes, with each collector electrode being connected to the corresponding one of the collector electrodes of said second pair of pnp transistors, and emitter electrodes of said fourth pair of npn transistors connected to a second coltage supply of opposite polarity from said first voltage supply, the collector electrode of one of said fourth pair of npn transistors being connected to its base electrode, the collector electrode of the other of said fourth pair of npn transistors being connected to said output means.
Claim 6
Dependent Claim
41 words
The differential amplifier according to claim 2, in which a capacitor is connected between the commonly connected base electrodes of said fourth pair of npn transistors and the second voltage supply to provide a phase-compensated output signal at the output means.
Claim 7
Dependent Claim
20 words
The differential amplifier according to claim 1, wherein all of said circuit elements are formed on a monolithic semiconductor substrate.
Claim 8
Dependent Claim
37 words
The differential amplifier according to claim 1, in which said emitter electrodes of said first pair of npn transistors are connected through respective resistors with the emitter electrodes of said second and third pairs of pnp transistors.
Claim 9
Dependent Claim
42 words
The differential amplifier according to claim 1, in which said bias circuit means comprises an npn transistor having a base adapted to receive a bias control signal and a collector connected to said base electrodes of said third pair of pnp transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-21 | 1981-05-23 | 1981-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-21 | 1985-05-23 | 1985-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-21 | 1989-05-23 | 1989-11-22 | $7700.00 | Window Closed / Lapsed |