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US4056819A
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Address converter
Assignee: Wincor Nixdorf International GmbH
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Filing: 1976-02-04
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Granted: 1977-11-01
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Expires: 1996-02-04
Abstract
Abstract An address converter for converting first addresses into second addresses which are fed to a memory of the data processing device, where the first addresses contain first and second address words and the second addresses contain third and fourth address words, the address words representing binary numbers, employs a comparator which is supplied with the first address word and a predetermined binary number and which is responsive thereto to emit a binary signal which assumes a first or a second binary value when the first address word is smaller than, or is not smaller than, respectively, the binary number, a transfer switch which assumes a first condition and a second condition when the binary signal assumes the first and second binary values, respectively, and which in the first and second positions, respectively, switches through the first address word or the binary number as a third address word, respectively, and an allocator which is supplied with the first and the second address words and which emits the fourth address word to the memory.
Inventors
- 👤 Eberhard Lukas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:31
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
192 words
An address converter for converting first addresses into second addresses which are fed to a memory of a data processing device, wherein the first addresses contain first and second address words and the second addresses contain third and fourth address words, said address converter comprising: a comparator for receiving a first address word and a predetermined binary number and responsive thereto to provide a first binary value when the first address word is less than the predetermined binary number and a second binary value when the first address word is not less than the predetermined binary number; transfer switch means for receiving the first address word and the predetermined binary number, said transfer switch means connected to the memory and connected to and operated by said comparator to selectively feed the first address word and the predetermined binary number to the memory as a third address word in response to the first and second binary values, respectively; and an allocator for receiving the first and second address words, said allocator connected to the memory and responsive to the first and second address words to feed a fourth address word to the memory.
Claim 2
Dependent Claim
192 words
An address converter for converting first addresses into second addresses which are fed to a memory of a data processing device, wherein the first addresses contain first and second address words and the second addresses contain third and fourth address words, said address converter comprising: a comparator for receiving a first address word and a predetermined binary number and responsive thereto to provide a first binary value when the first address word is less than the predetermined binary number and a second binary value when the first address word is not less than the predetermined binary number; transfer switch means for receiving the first address word and the predetermined binary number, said transfer switch means connected to the memory and connected to and operated by said comparator to selectively feed the first address word and the predetermined binary number to the memory as a third address word in response to the first and second binary values, respectively; and an allocator for receiving the first and second address words, said allocator connected to the memory and responsive to the first and second address words to feed a fourth address word to the memory.
Claim 3
Dependent Claim
41 words
The address converter set forth in claim 1, wherein said allocator comprises a modulo-R adder which receives the first and second address words and emits the fourth address word, where R indicates the range of values of the fourth address word.
Claim 4
Dependent Claim
125 words
The address converter set forth in claim 2, wherein said modulo-R adder includes first and second inputs and an output, and said allocator further comprises a subtracter and other transfer switch means, said subtracter including an output connected to said first input of said modulo-R adder and receiving and providing the difference between the first address word and the predetermined binary number, said other transfer switch means connected to receive the second address word, to said output of said modulo-R adder, to the memory and connected to and operated by said comparator to selectively feed the second address word and the output signals of the modulo-R adder to the memory as the fourth address word in response to the first and second binary values, respectively.
Claim 5
Dependent Claim
36 words
The address converter set forth in claim 3, wherein said comparator, said transfer switch means, said modulo-R adder, said subtracter and said other transfer switch means are constructed in the form of binary logic linking elements.
Claim 6
Dependent Claim
159 words
The address converter set forth in claim 1, comprising: a second comparator receiving the second address word and a second predetermined binary number and responsive thereto to provide a first binary value when the second address word is less than the maximum value of fourth address word which corresponds to the second predetermined binary number, and a second binary value when the second address word is not less than the second predetermined binary number; a modulo-N adder for receiving the first address word and the first-mentioned predetermined binary number increased by one, where N indicates the range of values of the third address words; and other transfer switch means connected to said second comparator and to the first-mentioned transfer switch means and connected to selectively receive and feed to the first-mentioned transfer switch means the first address word and the output of said modulo-N adder in response to the first and second binary values, respectively, from said second comparator.
Claim 7
Dependent Claim
58 words
The address converter set forth in claim 5, and further comprising: a modulo-B adder connected ahead of said modulo-N adder to receive and modulo-B convert the first address word before modulo-N conversion and feeding to said other transfer switch means, where B is equal to the difference between N and the first-mentioned predetermined binary number increased by one.
Claim 8
Dependent Claim
28 words
The address converter set forth in claim 6, wherein said comparators, said transfer switch means and said adders are constructed in the form of binary logic linking elements.
References Cited (Backward Citations)
US3425039A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |