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US4056809A Expired / Lapsed US ⏱️ 0.0 years remaining

Fast table lookup apparatus for reading memory

Assignee: Data Flo Corp
•
Filing: 1975-04-30
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Granted: 1977-11-01
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Expires: 1995-04-30
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Abstract

Abstract Fast Table Lookup Apparatus For Reading Memory is disclosed for use in conjunction with a logic bus, a memory device, a microprocessor of the type which provides an output logic signal to the bus comprising the contents of an internal register and which includes apparatus for immediately reading the logic signals on the bus into the internal register of the microprocessor, including logic which is external to the microprocessor, for recognizing when the microprocessor provides such a logic signal output and for utilizing the register contents available to address a location within the memory device to cause the substitution of the contents of the memory location within the memory device, which conforms to the microprocessor internal register contents, for the contents of the microprocessor internal register on the bus, and all in sufficient time for the memory location contents to be read into the microprocessor as a part of the next input to the microprocessor.

Inventors

  • 👤 John S. Hoerning
  • 👤 Richard P. Halverson
  • 👤 Darrell E. Nelson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 20:50
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 201 words
Fast table lookup apparatus for reading memory, comprising in combination: a logic bus; a memory device; a microprocessor of the type which provides an output logic signal to the bus comprising the contents of an internal register and which includes means for immediately reading logic signals on the bus into the internal register of the microprocessor; logic means, external to the microprocessor, for recognizing when the microprocessor provides the logic signal output comprising the contents of the internal register and for using the register contents available to address a location within the memory device and for substituting the contents of the memory location within the memory device, conforming to the microprocessor internal register contents, for the microprocessor internal register contents on the bus in time for the memory location contents to be read into the microprocessor as a part of the next input to the microprocessor; means for providing an electrical connection between the logic bus and the memory device; means for providing an electrical connection between the logic bus and the external logic; means for providing an electrical connection between the external logic and the memory device; means for providing an electrical connection between the logic bus and the microprocessor.
Claim 2
Dependent Claim 201 words
Fast table lookup apparatus for reading memory, comprising in combination: a logic bus; a memory device; a microprocessor of the type which provides an output logic signal to the bus comprising the contents of an internal register and which includes means for immediately reading logic signals on the bus into the internal register of the microprocessor; logic means, external to the microprocessor, for recognizing when the microprocessor provides the logic signal output comprising the contents of the internal register and for using the register contents available to address a location within the memory device and for substituting the contents of the memory location within the memory device, conforming to the microprocessor internal register contents, for the microprocessor internal register contents on the bus in time for the memory location contents to be read into the microprocessor as a part of the next input to the microprocessor; means for providing an electrical connection between the logic bus and the memory device; means for providing an electrical connection between the logic bus and the external logic; means for providing an electrical connection between the external logic and the memory device; means for providing an electrical connection between the logic bus and the microprocessor.

References Cited (Backward Citations)

US3656178A Cited
US3675211A Cited
US3694813A Cited
US3701108A Cited
US3717851A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-10-31 1981-05-02 1981-11-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-10-31 1985-05-02 1985-11-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-10-31 1989-05-02 1989-11-01 $7700.00 Window Closed / Lapsed

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