Code processor for variable-length dependent codes

Claim 2

A processor for encoding a fixed-length code word of a code alphabet wherein all the code words have the same number of code elements into a variable-length code word of a code alphabet wherein the code words have different numbers of code elements, and decoding a variable-length code word into a fixed-length code word comprising: a first memory unit having stored therein all the fixed-length code words of a code alphabet, each of said fixed-length code words being stored in combination with M address words where M is an integer, each of said M address words being assigned into a separate one of M code groups, each of said fixed length code words also being stored in combination with a code group number designating one of said M code groups and a coding set number designating a coding set, a second memory unit having stored therein variable-length code words of a code alphabet, said variable-length code words being stored in N separate coding sets where N is an integer, each of said variable-length code words in said coding sets being stored in combination with a coding set number indicating the coding set and an address word corresponding to an address word in said first memory unit, first input means connected to said first memory unit for comparing an input fixed length code word of said code alphabet with said fixed length code words stored in said first memory unit for obtaining a match on a corresponding one of said stored fixed-length code words, first output means for reading out from a previously selected one of Said M code groups of said first memory unit the address word stored in combination with said matched fixed-length code word, second input means connected to said second memory unit for comparing said address word read out from said first memory unit and a previously selected coding set number with said address words and said coding set numbers stored in said second memory unit for obtaining a match on a corresponding one address word and coding set number, and second output means for reading out of said second memory unit said variable length code word stored in combination with said matched address word and coding set number.

Claim 3

A processor according to claim 1 wherein said first output means also reads out the code group number and coding set number stored in combination with said matched fixed-length code word in said first memory unit, and further including means for storing said code group number and said coding set number read out of said first memory unit for designating one of said M code groups and one of said N coding sets for use with a subsequent input fixed-length code word.

Claim 4

A processor according to claim 1 wherein said second memory unit has stored therein a length indicating word stored in combination with each of said variable-length code words for indicating the number of code elements in said variable-length code word stored in combination therewith, and said second output means further including means for transmitting from said second output means the code elements of said variable-length code word read out of said second memory unit, said number of code elements transmitted being controlled by said length indicating word stored in combination therewith.

Claim 5

A processor according to claim 1 wherein said first memory unit is a two-state associative memory device and wherein said second memory unit is a three-state associative memory device.

Claim 6

A processor according to claim 1 further including means connected to said second memory unit for comparing an input variable-length code word and a previously selected coding set number with said variable-length code words and said coding set numbers stored in said second memory unit for obtaining a match on a corresponding variable-length code word and coding set number, means for reading out of said second memory unit said address word stored in combination with said matched variable-length code word and coding set number, means for comparing said address word read out of said second memory unit with the address words stored in a previously selected one of said M code groups in said first memory unit for obtaining a match on one of said address words, and means for reading out of said first memory unit the fixed-length code word stored in combination with said matched address word.

Claim 7

A processor according to claim 5 wherein said means for reading out said fixed-length code word from said first memory unit also reads out the code group number and coding set number stored in combination with said matched address word, and further including means for storing said code group number and coding set number read out of said first memory unit for designating one of said M code groups and one of said N coding sets for use with a subsequent input variable length word.

Claim 8

A processor according to claim 5 wherein said second memory unit has stored therein a length indicating word stored in combination with each of said variable-length code words for indicating the number of code elements in said variable-length code word stored in combination therewith, and wherein said means for comparing said input variable-length code word in said second memory unit further includes means for removing from said comparing means the code elements of said input variable-length code word, said number of code elements removed from said comparing means being controlled by said length indicating word stored in combination with said matched corresponding variable-length cOde word.

Claim 9

A processor for encoding a fixed-length code sword of a code alphabet wherein all the code words have the same number of code elements into a variable-length code word of a code alphabet wherein the code words have different numbers of code elements, and decoding a variable-length code word into a fixed-length code word comprising, a first associative memory device having a plurality of storage locations functionally arranged in rows and columns, said storage locations including two-state storage elements, a first column of said first memory having fixed-length code words of a code alphabet stored on separate rows thereof, M columns of said first memory each having address words stored in separate rows thereof, a further column of said first memory having code group number stored in separate rows thereof, a still further column of said first memory having coding set numbers stored in separate rows thereof such that each row of said first memory contains a fixed-length code word, M address words, a code group number and a coding set number, a second associative memory device having a plurality of storage locations functionally arranged in rows and columns, a first one of said columns having rows of storage locations including three-state storage elements, said first one of said columns of said second memory having the variable-length code words of a variable-length code alphabet arranged in N coding sets and stored in separate rows thereof, a second column of said second memory having the coding set numbers of said coding sets stored in storage locations in separate rows thereof, a third column of said second memory having length words stored in storage locations in separate rows thereof, each of said length words indicating the numbers of code elements of the variable-length code word stored in the same row, a fourth column of said second memory having address words stored in storage locations in separate rows thereof, said address words corresponding to said address words stored in said first memory, first input means connected to said first memory device for comparing an input fixed-length code word of said code alphabet with said fixed-length code words in said first column for obtaining a match with a corresponding fixed-length word in a row, first output means connected to said first memory device for reading out from a previously selected one of said M columns the address word stored in said matched row thereof, second input means connected to said second memory device for comparing said address word read out from said first memory device and a previously selected coding set number with said address words stored in said fourth column and said coding set numbers stored in said second column of said second memory device for obtaining a match on corresponding words in a row, and second output means connected to said second memory device for reading out from said first column thereof the variable-length code word stored in said matched row thereof.

Claim 10

A processor for encoding a fixed-length code sword of a code alphabet wherein all the code words have the same number of code elements into a variable-length code word of a code alphabet wherein the code words have different numbers of code elements, and decoding a variable-length code word into a fixed-length code word comprising, a first associative memory device having a plurality of storage locations functionally arranged in rows and columns, said storage locations including two-state storage elements, a first column of said first memory having fixed-length code words of a code alphabet stored on separate rows thereof, M columns of said first memory each having address words stored in separate rows thereof, a further column of said first memory having code group number stored in separate rows thereof, a still further column of said first memory having coding set numbers stored in separate rows thereof such that each row of said first memory contains a fixed-length code word, M address words, a code group number and a coding set number, a second associative memory device having a plurality of storage locations functionally arranged in rows and columns, a first one of said columns having rows of storage locations including three-state storage elements, said first one of said columns of said second memory having the variable-length code words of a variable-length code alphabet arranged in N coding sets and stored in separate rows thereof, a second column of said second memory having the coding set numbers of said coding sets stored in storage locations in separate rows thereof, a third column of said second memory having length words stored in storage locations in separate rows thereof, each of said length words indicating the numbers of code elements of the variable-length code word stored in the same row, a fourth column of said second memory having address words stored in storage locations in separate rows thereof, said address words corresponding to said address words stored in said first memory, first input means connected to said first memory device for comparing an input fixed-length code word of said code alphabet with said fixed-length code words in said first column for obtaining a match with a corresponding fixed-length word in a row, first output means connected to said first memory device for reading out from a previously selected one of said M columns the address word stored in said matched row thereof, second input means connected to said second memory device for comparing said address word read out from said first memory device and a previously selected coding set number with said address words stored in said fourth column and said coding set numbers stored in said second column of said second memory device for obtaining a match on corresponding words in a row, and second output means connected to said second memory device for reading out from said first column thereof the variable-length code word stored in said matched row thereof.

Claim 11

A processor according to claim 8 wherein said first output means also reads out from said further column the code group number stored in said matched row and from said still further column the coding set number stored in said matched row, and further including means for storing said code group number and coding set number read out of said first memory device for designating one of said M code groups and one of said N coding sets for use with a subsequent input fixed-length code word.

Claim 12

A processor according to claim 8 wherein said second output means also reads out from said third column of said second memory device the length indicating word stored in said matched row, said second output means further including means for transmitting from said second output means the code elements of said variable-length code word read out of said second memory unit, said number of code elements transmitted being controlled by Said length indicating word from said matched row.

Claim 13

A processor according to claim 8 further including means connected to said second memory device for comparing an input variable-length code word of said code alphabet with said variable-length code words in said first one of said columns of said second memory device and for comparing a previously selected coding set number with the coding set numbers stored in said second column for obtaining a match with a corresponding variable-length code word and coding set number in a row, means for reading out the address word stored in said matched row, means for comparing said address word read out of said second memory device with the address words stored in a previously selected one of said M columns of said first memory device for obtaining a match on a row thereof, and means for reading out of said first column of said first memory device the fixed-length code word stored in said matched row.

Claim 14

A processor according to claim 11 wherein said means for reading out said fixed-length code word from said matching row of said first memory device also reads out the code group number and coding set number stored in said matched row, and further including means for storing said code group number and said coding set number read out of said matched row for designating one of said M columns of said first memory device and one of said N coding sets of said second memory device for use with a subsequent input variable-length word.

Claim 17

A method according to claim 13 also including the steps of reading out the code group number and coding set number stored in combination with said matched fixed-length code word in said first memory unit, and storing said code group number and said coding set number read out of said first memory unit for designating one of said M code groups and one of said N coding sets for use with a subsequent input fixed-length code word.

Claim 18

A method according to claim 13 further including the steps of comparing an input variable length code word and a previously selected coding set number with said variable-length code words and said coding set numbers stored in said second memory unit for obtaining a match on a corresponding variable-length code word and coding set number, reading out said address word stored in combination with said matched variable-length code word and coding set number, comparing said address word read out of said second memory unit with the address words stored in a previously selected one of said M code groups in said first memory unit for obtaining a match on one of said address words, and reading out of said first memory unit the fixed-length code word stored in combination with said matched address word.

Claim 19

A method according to claim 15 further including the steps of reading out the code group number and coding set number stored in combination with said matched address word, and storing said code group number and coding set number read out of said first memory unit for designating one of said M code groups and one of said N coding sets for use with a subsequent input variable-length word.