Digital tone generator

Claim 2

A digital tone generator comprising: first means to generate a reference square wave signal having a stable given frequency; second means coupled to said first means to provide a plurality of square wave signals each having a different predetermined frequency, each of said predetermined frequencies having a different predetermined relationship to said given frequency; third means coupled to said second means to select at least one of said plurality of square wave signals; and fourth means coupled to said second means responsive only to said selected one of said plurality of square wave signals to provide as an output signal of said generator one sine wave tone having a frequency equal to said predetermined frequency divided by a given factor greater than two of said selected one of said plurality of square wave signals.

Claim 3

A generator according to claim 1, wherein said third means selects at least two of said plurality of square wave signals.

Claim 4

A generator according to claim 2, wherein said fourth means combines said two of said plurality of square wave signals and provides as an output signal of said generator two sine wave tones each having a frequency equal to a different one of said predetermined frequencies of said selected two of said plurality of square wave signals.

Claim 5

A generator according to claim 1, wherein said second means includes a logic circuit coupled to said first means.

Claim 6

A generator according to claim 4, wherein said third means includes a plurality of switches coupled to said logic circuit, each of said plurality of switches being associated with a different one of said plurality of square wave signals, an associated one of said plurality of switches coupling a voltage to said logic circuit to enable said logic circuit to select said associated one of said plurality of square wave signals.

Claim 7

A generator according to claim 5, wherein said fourth means includes a ring counter having a given number of stages coupled to said logic circuit responsive to said selected one of said plurality of square wave signals to divide the frequency of said selected one of said plurality of square wave signals by said given factor, a resistor network coupled to an output of predetermined ones of said stages, and a filter coupled to said resistor network to provide said one sine wave tone.

Claim 8

A generator according to claim 6, wherein said ring counter is a Johnson counter.

Claim 9

A generator according to claim 6, wherein said resistor network includes a plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages and a common point.

Claim 10

A generator according to claim 6, wherein said filter includes a capacitor coupled between said resistor network and ground potential.

Claim 11

A generator according to claim 6, wherein said ring counter is a Johnson counter having N stages, where N is an integer greater than one; said resistor network includes a plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages and a common point; and said filter includes a capacitor coupled between said common point and ground potential.

Claim 12

A generator according to claim 6, wherein said logic circuit includes a binary divider coupled to said first means, said divider having a plurality of output taps, a plurality of AND gates each coupled to appropriate ones of said plurality of output taps to provide a different one of said plurality of square wave signals and to an associated one of said plurality of switches to select said one of said plurality of square wave signals when said associated one of said plurality of switches is closed to couple a voltage to an associated one of said plurality of AND gates for enabling thereof to select said one of said plurality of square wave signals, an OR gate coupled to the outputs of each of said plurality of AND gates, and a one-shot multivibrator coupled to said OR gate, said divider and said ring counter to produce a pulse from said selected one of said plurality of square wave signals at the output of said OR gate to reset said divider and to shift said ring counter.

Claim 13

A generator according to claim 1, wherein said third means includes a plurality of switches coupled to said second means, each of said plurality of switches being associated with a different one of said plurality of square wave signals, an associated one of said plurality of switches coupling a voltage to said second means to enable said second means to select said associated one of said plurality of square wave signals.

Claim 14

A generator according to claim 12, wherein said fourth means includes a ring counter having a given number of stages coupled to said second means responsive to said selected one of said plurality of square wave signals to divide the frequency of said selected one of said plurality of square wave signals by said given factor, a resistor network coupled to an output of predetermined ones of said stages, and a filter coupled to said resistor network to provide said one sine wave tone.

Claim 15

A generator according to claim 13, wherein said ring counter is a Johnson counter.

Claim 16

A generator according to claim 13, wherein said resistor network includes a plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages and a common point.

Claim 17

A generator according to claim 13, wherein said filter includes a capacitor coupled between said resistor network and ground potential.

Claim 18

A generator according to claim 13, wherein said ring counter is a Johnson counter having N stages, where N is an integer greater than one; said resistor network includes a plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages and a common point; and said filter includes a capacitor coupled between said common point and ground potential.

Claim 19

A generator according to claim 13, wherein said second means includes a binary divider coupled to said first means, said divider having a plurality of output taps, a plurality of AND gates each coupled to appropriate ones of said plurality of output taps to provide a different one of said plurality of square wave signals and to an associated one of said plurality of switches to select said one of said plurality of square wave signals when said associated one of said plurality of switches is closed to couple a voltage to an associated one of said plurality of AND gates for enabling thereof to select said one of said plurality of square wave signals, an OR gate coupled to the outputs of each of said plurality of AND gates, and a one-shot multivibrator coupled to said OR gate, said divider and said ring counter to produce a pulse from said selected one of said plurality of square wave signals at the output of said OR gate to reset said divider and to shift said ring counter.

Claim 20

A generator according to claim 1, wherein said fourth means includes a ring counter having a given number of stages coupled to said first means responsive to said selected one of said plurality of square wave signals to divide the frequency of said selected one of said plurality of square wave signals by said given factor, a resistor network coupled to an output of predetermined ones of said stages, and a filter coupled to said resistor network to provide said one sine wave tone.

Claim 21

A generator according to claim 19, wherein said ring counter is a Johnson counter.

Claim 22

A generator according to claim 19, wherein said resistor network includes a plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages and a common point.

Claim 23

A generator according to claim 19, wherein said filter includes a capacitor coupled between said resistor network and ground potential.

Claim 24

A generator according to claim 19, wherein said ring counter is a Johnson counter having N stages, where N is an integer greater than one; said resistor network includes a plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages and a common point; and said filter includes a capacitor coupled between said common point and ground potential.

Claim 25

A generator according to claim 19, wherein said second means includes a binary divider coupled to said first means, said divider having a plurality of output taps, a plurality of AND gates each coupled to appropriate ones of said plurality of output taps to provide a different one of said plurality of square wave signals and to an associated one of said plurality of switches to select said one of said plurality of square wave signals when said associated one of said plurality of switches is closed to couple a voltage to an associated one of said plurality of AND gates for enabling thereof to select said one of said plurality of square wave signals, an OR gate coupled to the outputs of each of said plurality of AND gates, and a one-shot multivibrator coupled to said OR gate, said divider and said ring counter to produce a pulse from said selected one of said plurality of square wave signals at the output of said OR gate to reset said divider and to shift said ring counter.

Claim 26

A generator according to claim 1, wherein said second means includes a binary divider coupled to said first means, said divider having a plurality of output taps, a plurality of AND gates each coupled to appropriate ones of said plurality of output taps to provide a different one of said plurality of square wave signals and to an associated one of said plurality of switches to select said one of said plurality of square wave signals when said associated one of said plurality of switches is closed to couple a voltage to an associated one of said plurality of AND gates for enabling thereof to select said one of said plurality of square wave signals, an OR gate coupled to the outputs of each of said plurality of AND gates, and a one-shot multivibrator coupled to said OR gate, said divider and said ring counter to produce a pulse from said selected one of said plurality of square wave signals at the output of said OR gate to reset said divider and to shift said ring counter.

Claim 27

A generator according to claim 1, wherein said second means includes a first logic circuit coupled to said first means to provide one half of said plurality of square wave signals, and a second logic circuit coupled to said first means to provide the other half of said plurality of square wave signals.

Claim 28

A generator according to claim 26, wherein said third means includes a first plurality of switches coupled to said first logic circuit, each of said first plurality of switches being associated with a different one of said one half of said plurality of square wave signals, an associated one of said first plurality of switches coupling a voltage to said first logic circuit to select said associated one of said one half of said plurality of square wave signals, and a second plurality of switches coupled to said second logic circuit, each of said second plurality of switches being associated with a different one of said other half of said plurality of square wave signals, an associated one of said second plurality of switches coupling a voltage to said second logic circuit to select said associated one of said other half of said plurality of square wave signals.

Claim 29

A generator according to claim 27, wherein said fourth means includes a first ring counter having a given number of stages coupled to said first logic circuit responsive to said selected one of said one half of said plurality of square wave signals to divide the frequency of said selected one of said one half of said plurality of square wave signals by said given factor, a first resistor network coupled to an output of predetermined ones of said stages of said first ring counter, a filter coupled to said first resistor network to provide said one sine wave tone, a second ring counter having a given number of stages coupled to said second logic circuit responsive to said selected one of said other half of said plurality of square wave signals to divide the frequency of said selected one of said other half of said plurality of square wave signals by said given factor, and a second resistor network coupled to an output of predetermined ones of said stages of said second ring counter and said filter to provide a second sine wave tone having a frequency equal to said predetermined frequency divided by said given factor of said selected one of said other half of said plurality of square wave signals.

Claim 30

A generator according to claim 28, wherein each of said first and second ring counters include a Johnson counter.

Claim 31

A generator according to claim 28, wherein said first resistor network includes a first plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages of said first ring counter and a common point; and said second resistor network includes a second plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages of said second ring counter and said common point.

Claim 32

A generator according to claim 28, wherein said filter includes a capacitor coupled between said first and second resistor networks and ground potential.

Claim 33

A generator according to claim 28, wherein each of said first and second ring counters is a Johnson counter having N stages, where N is an integer greater than one; said first resistor network includes a first plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages of one of said Johnson counters and a common point; said second resistor network includes a second plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages of the other of said Johnson counters and said common point; and said filter includes a capacitor coupled between said common point and ground potential.

Claim 34

A generator according to claim 28, wherein said first logic circuit includes a first binary divider coupled to said first means, said first divider having a first plurality of output taps, a first plurality of AND gates each coupled to appropriate ones of said first plurality of output taps to provide a different one of said one half of said plurality of square wave signals and to an associated one of said first plurality of switches to select said one of said one half of said plurality of square wave signals when said associated one of said first plurality of switches is closed to couple a voltage to an associated one of said first plurality of said AND gates for enabling thereof to select said one of said one half of said plurality of square wave signals, a first OR gate coupled to the outputs of each of said first plurality of AND gates, and a first one shot multivibrator coupled to said first OR gate, said first divider and said first ring counter to produce a pulse from said selected one of said one half of said plurality of square wave signals at the output of said first OR gate to reset said first divider and to shift said first ring counter; and said second logic circuit includes a second binary divider coupled to said first means, said second divider having a second plurality of output taps, a second plurality of AND gates each coupled to appropriate ones of said second plurality of output taps to provide a different one of said other half of said plurality of square wave signals and to an associated one of said second plurality of switches to select said one of said other half of said plurality of square wave signals when said associated one of said second plurality of switches is closed to couple a voltage to an associated one of said second plurality of AND gates for enabling thereof to select said one of said other half of said plurality of square wave signals, a second OR gate coupled to the outputs of each of said second plurality of AND gates, and a second one-shot multivibrator coupled to said second OR gate, said second divider and said second ring counter to produce a pulse from said selected one of said other half of said plurality of square wave signals at the output of said second OR gate to reset said second divider and to shift said second ring counter.

Claim 35

A generator according to claim 1, wherein said third means includes a first plurality of switches coupled to said second means, each of said first plurality of switches being associated with a different one of one half of said plurality of square wave signals, an associated one of said first plurality of switches coupling a voltage to said second means to select said associated one of said one half of said plurality of square wave signals, and a second plurality of switches coupled to said second means, each of said second plurality of switches being associated with a different one of the other half of said plurality of square wave signals, an associated one of said second plurality of switches coupling a voltage to said second means to select said associated one of said other half of said plurality of square wave signals.

Claim 36

A generator according to claim 1, wherein said fourth means includes a first ring counter having a given number of stages coupled to said second means responsive to said selected one of one half of said plurality of square wave signals to divide the frequency of said selected one of said one half of said plurality of square wave signals by said given factor, a first resistor network coupled to an output of predetermined ones of said stages of said first ring counter, a filter coupled to said first resistor network to provide said one sine wave tone, a second ring counter having a given number of stages coupled to said second means responsive to said selected one of the other half of said plurality of square wave signals to divide the frequency of said selected one of said other half of said plurality of square wave signals by said given factor, and a second resistor network coupled to an output of predetermined ones of said stages of said second ring counter and said filter to provide a second sine wave tone having a frequency equal to said predetermined frequency divided by said given factor of said selected one of said other half of said plurality of square wave signals.

Claim 37

A generator according to claim 35, wherein each of said first and second ring counters include a Johnson counter.

Claim 38

A generator according to claim 35, wherein said first resistor network includes a first plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages of said first ring counter and a common point; and said second resistor network includes a second plurality of parallel resistors each coupled between said output of one of said predetermined ones of said stages of said second ring counter and said common point.

Claim 39

A generator according to claim 35, wherein said filter includes a capacitor coupled between said first and second resistor networks and ground potential.

Claim 40

A generator according to claim 35, wherein each of said first and second ring counters is a Johnson counter having N stages, where N is an integer greater than one; said first resistor network includes a first plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages of one of said Johnson counters and a common point; said second resistor network includes a second plurality of parallel resistors each coupled between an output of one of the last (N - 1) of said N stages of the other of said Johnson counters and said common point; and said filter includes a capacitor coupled between said common point and ground potential.

Claim 41

A generator according to claim 35, wherein said second means includes a first binary divider coupled to said first means, said first divider having a first plurality of output taps, a first plurality of AND gates each coupled to appropriate ones of said first plurality of output taps to provide a different one of said one half of said plurality of square wave signals and to an associated one of said first plurality of switches to select said one of said one half of said plurality of square wave signals when said associated one of said first plurality of switches is closed to couple a voltage to an associated one of said first plurality of said AND gates for enabling thereof to select said one of said one half of said plurality of square wave signals, a first OR gate coupled to the outputs of each of said first plurality of AND gates, a first one-shot multivibrator coupled to said first OR gate, said first divider and said first ring counter to produce a pulse from said selected one of said one half of said plurality of square wave signals at the output of said first OR gate to reset said first divider and to shift said first ring counter, a second binary divider coupled to said first means, said second divider having a second plurality of output taps, a second plurality of AND gates each coupled to appropriate ones of said second plurality of output taps to provide a different one of said other half of said plurality of square wave signals and to an associated one of said second plurality of switches to select said one of said other half of said plurality of square wave signals when said associated one of said second plurality of switches is closed to couple a voltage to an associated one of said second plurality of AND gates for enabling thereof to select said one of said other half of said plurality of square wave signals, a second OR gate coupled to the outputs of each of said second plurality of AND gates, and a second one-shot multivibrator coupled to said second OR gate, said second divider and said second ring counter to produce a pulse from said selected one of said other half of said plurality of square wave signals at the output of said second OR gate to reset said second divider and to shift said second ring counter.

Claim 42

A generator according to claim 1, wherein said second means includes a first binary divider coupled to said first means, said first divider having a first plurality of output taps, a first plurality of AND gates each coupled to appropriate ones of said first plurality of output taps to provide a different one of said one half of said plurality of square wave signals and to an associated one of said first plurality of switches to select said one of said one half of said plurality of square wave signals when said associated one of said first plurality of switches is closed to couple a voltage to an associated one of said first plurality of said AND gates for enabling thereof to select said one of said one half of said plurality of square wave signals, a first OR gate coupled to the outputs of each of said first plurality of AND gates, a first one shot multivibrator coupled to said first OR gate, said first divider and said first ring counter to produce a pulse from said selected one of said one half of said plurality of square wave signals at the output of said first OR gate to reset said first divider and to shift said first ring counter, a second binary divider coupled to said first means, said second divider having a second plurality of output taps, a second plurality of AND gates each coupled to appropriate ones of said second plurality of output taps to provide a different one of said other half of said plurality of square wave signals and to an associated one of said second plurality of switches to select said one of said other half of said plurality of square wave signals when said associated one of said second plurality of switches is closed to couple a voltage to an associated one of said second plurality of AND gates for enabling thereof to select said one of said other half of said plurality of square wave signals, a second OR gate coupled to the outputs of each of said second plurality of AND gates, and a second one-shot multivibrator coupled to said second OR gate, said second divider and said second ring counter to produce a pulse from said selected one of said other half of said plurality of square wave signals at the output of said second OR gate to reset said second divider and to shift said second ring counter.