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US4055884A
Expired / Lapsed
US
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Fabrication of power field effect transistors and the resulting structures
Assignee: International Business Machines Corp
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Filing: 1976-12-13
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Granted: 1977-11-01
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Expires: 1996-12-13
Abstract
Abstract The fabrication method provides a power metal-oxide-semiconductor field-effect transistor (MOSFET) having high switching speed capabilities. The high switching speed is facilitated by narrow channel length which is defined by the difference in lateral diffusion junctions of the P substrate and N source diffusions. The high current capability is produced by the large channel width. The high voltage capability is caused by the use of FET substrate P diffusions designed to be located apart from one another by very small distances. Unbiased or floating P diffusions are designed to flank the outer peripheries of P substrate diffusions. The close proximity of the adjacent P substrate diffusions reduces the electric field in the curvature portion of the P diffusion junctions in the N - silicon body at their inner peripheries, while the presence of the unbiased P diffusions at the appropriate distance from the outer peripheries of P substrate diffusions reduces the electric field in the curvature region of the P substrate diffusions at their outer peripheries. The N silicon body forms the drain region.
Inventors
- 👤 Chakrapani Gajanan Jambotkar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10D62/124; H10D62/126; H10D62/127
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
114 words
Method for fabrication of MOSFET devices having high current and high voltage characteristics comprising: providing an N substrate; forming a plurality of P regions in said substrate; forming N regions in said P regions; forming precise and desired gate insulator regions above peripheries of inner said P regions while allowing outermost annular P regions to remain under a blanket fieled insulator; forming source contacts to the N regions within said inner P regions, forming gates over the said gate insulator regions, and forming the common drain region contact on the backside of the N+ substrate; and allowing the said outermost annular P regions to remain unbiased to thereby improve the drain-to-substrate reverse breakdown voltage.
Claim 2
Dependent Claim
114 words
Method for fabrication of MOSFET devices having high current and high voltage characteristics comprising: providing an N substrate; forming a plurality of P regions in said substrate; forming N regions in said P regions; forming precise and desired gate insulator regions above peripheries of inner said P regions while allowing outermost annular P regions to remain under a blanket fieled insulator; forming source contacts to the N regions within said inner P regions, forming gates over the said gate insulator regions, and forming the common drain region contact on the backside of the N+ substrate; and allowing the said outermost annular P regions to remain unbiased to thereby improve the drain-to-substrate reverse breakdown voltage.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein said substrate in in part an epitaxial layer and said P and N regions are formed in said epitaxial layer.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein said epitaxial layer is N- and the remaining portion of said substrate in N+.
Claim 5
Dependent Claim
64 words
The method of claim 1 wherein the said P regions were formed by diffusion through openings in an insulator layer, a second insulator layer formed thereafter and made to cover the portion of said openings that will partly become said substrate contacts, and said N regions formed by diffusion through the said openings in said insulator layer as modified by said second insulator films.
Claim 6
Dependent Claim
37 words
The method of claim 4 wherein the said insulator layer is silicon dioxide, said second insulator layer is silicon nitride and a silicon dioxide film is thermally grown while simultaneously driving in said P and N regions.
Claim 7
Dependent Claim
27 words
The method of claim 4 wherein said P junction depth is between about 2 to 7 micrometers and said N junction between about 1 to 4 micrometers.
Claim 8
Dependent Claim
20 words
The method of claim 1 wherein the channel length under the said gates is between about 1 to 5 micrometers.
Claim 9
Dependent Claim
22 words
The method of claim 6 wherein the distance between pairs of said inner P regions is between about 4 to 10 micrometers.
Claim 10
Dependent Claim
32 words
The method of claim 8 wherein said outermost annular P regions have a distance between about 20 to 50 micrometers between one another and the outer peripheries of the inner P regions.
Claim 11
Dependent Claim
120 words
Method for fabrication of MOSFET devices having high current and high voltage characteristics comprising: providing a P+ substrate having a P- epitaxial layer; forming a plurality of N regions in said epitaxial layer; forming P regions in said N regions; forming precise and desired gate insulator regions above peripheries of inner said N regions while allowing outermost annular N regions to remain under a blanket field insulator; forming source contacts to the P regions within said inner N regions, forming gates over the said gate insulator regions, and forming the common drain region contact on the backside of the P+ substrate; and allowing the said outermost annular N regions to remain unbiased to thereby improve the drain-to-substrate reverse breakdown voltage.
Claim 12
Dependent Claim
120 words
Method for fabrication of MOSFET devices having high current and high voltage characteristics comprising: providing a P+ substrate having a P- epitaxial layer; forming a plurality of N regions in said epitaxial layer; forming P regions in said N regions; forming precise and desired gate insulator regions above peripheries of inner said N regions while allowing outermost annular N regions to remain under a blanket field insulator; forming source contacts to the P regions within said inner N regions, forming gates over the said gate insulator regions, and forming the common drain region contact on the backside of the P+ substrate; and allowing the said outermost annular N regions to remain unbiased to thereby improve the drain-to-substrate reverse breakdown voltage.
Claim 13
Dependent Claim
37 words
The method of claim 10 wherein the channel length under the said gates is between about 1 to 5 micrometers and the distance between pairs of said inner N regions is between about 4 to 10 micrometers.
References Cited (Backward Citations)
US3199002A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |