US4054989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
Assignee: International Business Machines Corp
•
Filing: 1975-11-06
•
Granted: 1977-10-25
•
Expires: 1995-11-06
Abstract
Abstract An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.
Inventors
- 👤 Irving T. Ho
- 👤 Jacob Riseman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/0223; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D99/00; H10P; H10P14/00; H10P14/60; H10P14/61; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
181 words
A method of fabricating a field effect transistor comprising the steps of: a. forming a thin layer of oxide on a wafer of monocrystalline silicon, b. depositing a layer of conductive polycrystalline silicon on said thin layer of oxide, c. forming a layer of silicon nitride on said polycrystalline layer, d. within at least the area of said wafer where said field effect transistor is to be fabricated, removing portions of said silicon nitride layer to form a silicon nitride mask over said polysilicon layer, said mask in said area covering only the region to be the gate structure of said field effect transistor, e. oxidizing all said polysilicon layer not covered by said silicon nitride mask to form a thick oxide layer thicker than said polysilicon layer, f. opening holes within said thick oxide layer on opposite sides of said gate structure, g. introducing impurities into the surface of said monocrystalline silicon layer exposed by said openings to form the drain and source regions of said field effect transistor, and h. forming conductive contacts to said source and drain regions.
Claim 2
Independent Claim
181 words
A method of fabricating a field effect transistor comprising the steps of: a. forming a thin layer of oxide on a wafer of monocrystalline silicon, b. depositing a layer of conductive polycrystalline silicon on said thin layer of oxide, c. forming a layer of silicon nitride on said polycrystalline layer, d. within at least the area of said wafer where said field effect transistor is to be fabricated, removing portions of said silicon nitride layer to form a silicon nitride mask over said polysilicon layer, said mask in said area covering only the region to be the gate structure of said field effect transistor, e. oxidizing all said polysilicon layer not covered by said silicon nitride mask to form a thick oxide layer thicker than said polysilicon layer, f. opening holes within said thick oxide layer on opposite sides of said gate structure, g. introducing impurities into the surface of said monocrystalline silicon layer exposed by said openings to form the drain and source regions of said field effect transistor, and h. forming conductive contacts to said source and drain regions.
Claim 3
Dependent Claim
88 words
The method as claimed in claim 1 further comprising, prior to the formation of said thin layer, the steps of etching the surface of said monocrystalline area to form an etched surface ring surrounding a region of said monocrystalline silicon, and oxidizing said etched surface ring to form an oxide ring around said region, said oxide ring being substantially flush with said monocrystalline surface, said gate structure being formed on the monocrystalline surface within said region, and said drain and source diffused regions being formed within said region.
Claim 4
Dependent Claim
87 words
The method as claimed in claim 2 further comprising, prior to the formation of said oxide ring, the steps of, epitaxially growing a layer of single crystal silicon onto a substrate of single crystal silicon, said epitaxial and substrate layers being of the same type conductivity and said epitaxial layer being significantly more resistive than said substrate layer, wherein said epitaxial and substrate layer together comprise said wafer of monocrystalline silicon and wherein said oxide ring extends all the way through said epitaxial layer into said substrate.
Claim 5
Independent Claim
159 words
A method of fabricating a field effect transistor comprising the steps of: a. forming a thin layer of oxide on a wafer of monocrystalline silicon, b. depositing a layer of conductive polycrystalline silicon on said thin layer of oxide, c. forming a layer of silicon nitride on said polycrystalline layer, d. within at least the area of said wafer where said field effect transistor is to be fabricated, removing portions of said silicon nitride layer to form a silicon nitride mas over said polysilicon layer, said mask in said area covering only the region to be the gate structure of said field effect transistor, e. oxidizing all said polysilicon layer not covered by said silicon nitride mask to form a thick oxide layer thicker than said polysilicon layer, g. opening holes within said thick oxide layer on opposite side of said gate structure, and, g. introducing imputirites into the surface of said monocrystalline silicon layer exposed by said openings.
Claim 6
Independent Claim
159 words
A method of fabricating a field effect transistor comprising the steps of: a. forming a thin layer of oxide on a wafer of monocrystalline silicon, b. depositing a layer of conductive polycrystalline silicon on said thin layer of oxide, c. forming a layer of silicon nitride on said polycrystalline layer, d. within at least the area of said wafer where said field effect transistor is to be fabricated, removing portions of said silicon nitride layer to form a silicon nitride mas over said polysilicon layer, said mask in said area covering only the region to be the gate structure of said field effect transistor, e. oxidizing all said polysilicon layer not covered by said silicon nitride mask to form a thick oxide layer thicker than said polysilicon layer, g. opening holes within said thick oxide layer on opposite side of said gate structure, and, g. introducing imputirites into the surface of said monocrystalline silicon layer exposed by said openings.
References Cited (Backward Citations)
US3761327A
Cited
US3751722A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-24 | 1981-04-25 | 1981-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-24 | 1985-04-25 | 1985-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-24 | 1989-04-25 | 1989-10-25 | $7700.00 | Window Closed / Lapsed |