Band compression device

Claim 2

A band compression device for receiving input signals of predetermined frequency bandwidth and for delivering output signals of bandwidth n times narrower comprising: sampling means for sampling said input signals; storing means for storing at least two successive samples in a series of n successive samples; amplitude comparing means for comparing said samples taken in pairs and for providing a logic transfer control signal depending on each of said amplitude comparisons; an output memory for receiving the sample greatest in amplitude in said series and delivering said output signal; and control means connected to said storing means, said output memory and receiving said logic control signal for transferring said greatest of the compared samples to said output memory.

Claim 3

A device according to claim 1 wherein: said storing means comprises a first and a second memory connected in series, and said amplitude comparing means comprises a comparator circuit connected to the input and output of the second memory for providing said logic control signal in the form of a sampling control signal to the said second memory when the sample at the input to the second memory is greater than that of the sample at the output of the said second memory.

Claim 4

A device according to claim 1, wherein said control means comprises clock circuit means for delivering sampling control signals to said storing means and a divider circuit connected to said clock circuit means for delivering a control signal to the output memory at the end of each series of n successive samples.

Claim 5

A band compression device comprising, in series, a first memory, second memory and an output memory, each memory having a sample control input, a comparator circuit connected to the input and output of the second memory for giving a control signal when the amplitude of the sample at the input of the second memory is greater than that of the sample at the output of said second memory, and control circuit means comprising, a clock circuit having an output, a delay circuit and a divider circuit having an output, said clock delay and divider being connected in series, said clock circuit having its output connected to the sampling control input of the first memory, said divider circuit having its output connected to the sampling control input of the output memory, and AND circuit having two inputs and its output connected to the sampling control input of the second memory, one of its inputs connected to the output of the delay circuit, and the other input connected to an OR circuit having its inputs connected respectively to the output of the comparator circuit and to the output of the divider circuit.

Claim 6

A band compression device comprising, in series, a first memory, second memory and an output memory, each memory having a sample control input, a comparator circuit connected to the input and output of the second memory for giving a control signal when the amplitude of the sample at the input of the second memory is greater than that of the sample at the output of said second memory, and control circuit means comprising, a clock circuit having an output, a delay circuit and a divider circuit having an output, said clock delay and divider being connected in series, said clock circuit having its output connected to the sampling control input of the first memory, said divider circuit having its output connected to the sampling control input of the output memory, and AND circuit having two inputs and its output connected to the sampling control input of the second memory, one of its inputs connected to the output of the delay circuit, and the other input connected to an OR circuit having its inputs connected respectively to the output of the comparator circuit and to the output of the divider circuit.

Claim 7

A device according to claim 4, wherein the divider circuit is programmable to allow the compression ratio to be selected.

Claim 8

A device according to claim 1, wherein said storing and comparing means comprises a plurality of identical stages connected in series, each stage comprising a memory, a two-input multiplexer and a comparator circuit connected to the the multiplexer for applying to said multiplexer a control signal so that it will transmit to its output the greatest of the two signals applied to its inputs, the input signals of the device being applied to the input of the memory of the first stage and to one input of the multiplexer of all stages, the other input of the multiplexer being connected to the output of the memory, and the output of the multiplexer of each stage being connected to an input of the memory of the next stage.

Claim 9

A band compression device for receiving input signals, comprising in series a plurality of identical stages, each stage comprising a memory, a two-input multiplexer and a comparator circuit having its inputs connected to the inputs of the multiplexer for applying to said multiplexer a control signal so that it will transmit the greatest of the two signals applied to its inputs, the output of the memory being connected to one input of the multiplexer, the other input receiving the input signals for the device, said input signals being also applied to the input of the memory of the first stage and the output of the multiplexer of each stage being connected to the input of the memory of the next stage, an output memory connected to the output of the multiplexer of the last stage and a clock circuit for applying sampling control signals to all memories of the device.

Claim 10

A band compression device for receiving input signals, comprising in series a plurality of identical stages, each stage comprising a memory, a two-input multiplexer and a comparator circuit having its inputs connected to the inputs of the multiplexer for applying to said multiplexer a control signal so that it will transmit the greatest of the two signals applied to its inputs, the output of the memory being connected to one input of the multiplexer, the other input receiving the input signals for the device, said input signals being also applied to the input of the memory of the first stage and the output of the multiplexer of each stage being connected to the input of the memory of the next stage, an output memory connected to the output of the multiplexer of the last stage and a clock circuit for applying sampling control signals to all memories of the device.

Claim 11

A device according to claim 7, further comprising a decoding circuit having its outputs connected respectively to zero reset inputs of the memories, and means for applying to the input of the decoding circuit the digital number equal to the desired compression ratio.

Claim 12

A device according to claim 8, further comprising in each stage an AND circuit which is inserted between the comparator and the control input of the multiplexer, a decoding circuit having outputs which are respectively connected to the AND circuits and an input at which the desired compression ratio is set.