Patent US4052673A successfully refreshed from Google Patents.
US4052673A
Expired / Lapsed
US
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Combined controlled oscillator and frequency multiplier
Assignee: RCA Licensing Corp
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Filing: 1976-08-30
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Granted: 1977-10-04
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Expires: 1996-08-30
Abstract
Abstract A voltage controlled oscillator which, for example, may be utilized in a phase locked loop, includes an odd number (n) of cascaded COS-MOS inverter stages with a feedback path coupling the output of the last stage to the input of the first stage to form a ring configuration. The ring configuration oscillates at a frequency f 1 determined by the transconductances of the inverter stages and the shunt capacitances between the stages. Signals comprising impulses of current having frequency components at f 1 and 2f 1 flow through the power supply inputs of each of the stages as they successively are switched from one state to another. A frequency selective impedance path is coupled between a source of power supply voltage and the power supply inputs of each of the stages to develop a second signal having a frequency f 2 equal to a multiple nf 1 or 2nf 1 . The voltage applied to the commonly connected power supply inputs may be controlled to control f 1 and, consequently, f 2 .
Inventors
- 👤 Gerald Bernard Herzog
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:43
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03K; H03K7/00; H03K7/06; H03L7/08; H03L7/099; H03L7/0995; H04; H04N; H04N5/00; H04N5/44; H04N5/50
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
134 words
Apparatus comprising: means for coupling a first signal having a frequency f 1 to a circuit point; a number n of stages coupled in a cascaded configuration, said circuit point being an input to said cascaded configuration, each of said stages being, successively switched from a first state to a second state in response to said first signal each of said stages drawing power for a time duration shorter than the period of said first signal when it switches from one state to another; said number n of power coupling means for providing power to respective ones of said stages; a source of power; impedance means coupled between each of said power coupling means and said source of power for developing a second signal having at least a frequency component at nf 1 .
Claim 2
Dependent Claim
134 words
Apparatus comprising: means for coupling a first signal having a frequency f 1 to a circuit point; a number n of stages coupled in a cascaded configuration, said circuit point being an input to said cascaded configuration, each of said stages being, successively switched from a first state to a second state in response to said first signal each of said stages drawing power for a time duration shorter than the period of said first signal when it switches from one state to another; said number n of power coupling means for providing power to respective ones of said stages; a source of power; impedance means coupled between each of said power coupling means and said source of power for developing a second signal having at least a frequency component at nf 1 .
Claim 3
Dependent Claim
19 words
The apparatus recited in claim 1 wherein said second signal additionally has a frequency component at 2nf 1 .
Claim 4
Dependent Claim
22 words
The apparatus recited in claim 2 wherein said impedance means includes frequency selective means broadly tuned to said frequency nf 1 .
Claim 5
Dependent Claim
27 words
The apparatus recited in claim 2 wherein said impedance means includes frequency selective means broadly tuned to one of said frequencies nf 1 or 2nf 1 .
Claim 6
Dependent Claim
30 words
The apparatus recited in claim 2 wherein said impedance means includes frequency selective means and buffer means coupled between said frequency selective means and each of said power coupling means.
Claim 7
Dependent Claim
46 words
The apparatus recited in claim 5 further including means for generating a control signal for controlling said first frequency f 1 ; and wherein said buffer means includes a transistor arranged in an emitter-follower configuration, said control signal being coupled to the base of said transistor.
Claim 8
Dependent Claim
42 words
The apparatus recited in claim 1 wherein said stages each comprise signal inverting means; said number n is an odd number; and said signal inverting means are cascaded to form a ring configuration which oscillates at said first frequency f 1 .
Claim 9
Dependent Claim
23 words
The apparatus recited in claim 7 wherein said signal inverting stages comprise field effect transistors of opposite type coupled in a complementary configuration.
Claim 10
Dependent Claim
32 words
The apparatus recited in claim 7 further including control means for generating a control signal, said control signal being coupled to said ring configuration to control the frequency of said first signal.
Claim 11
Dependent Claim
24 words
The apparatus recited in claim 9 wherein said control means is coupled to said impedance means to control the power coupled to said stages.
Claim 12
Dependent Claim
68 words
The apparatus recited in claim 9 wherein said control means comprises a phase locked loop including a source of a frequency reference signal; means responsive to said frequency reference signal and to said first signal for generating an error signal representing the phase and frequency relationship between said frequency reference signal and said first signal; and means for deriving said control signal in response to said error signal.
Claim 13
Dependent Claim
31 words
The apparatus recited in claim 11 wherein said second signal is coupled to a means for combining said second signal and a radio frequency signal to derive an intermediate frequency signal.
Claim 14
Dependent Claim
15 words
The apparatus recited in claim 11 wherein said second signal is coupled to transmitting means.
Claim 15
Dependent Claim
27 words
The apparatus recited in claim 13 wherein said control means comprises means for controlling the amplitude of said control signal in response to an information bearing signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-03 | 1981-04-04 | 1981-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-03 | 1985-04-04 | 1985-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-03 | 1989-04-04 | 1989-10-04 | $7700.00 | Window Closed / Lapsed |