Semiconductor memory cell

Claim 1

A memory cell circuit provided in a semiconductor device having a semiconductor substrate of a first conductivity type except for selected regions thereof including first and second selected regions, said selected regions having a second conductivity type such that a semiconductor junction is formed between first conductivity portions of said substrate and each of said selected regions including a first semiconductor associated with said first selected region and a second semiconductor junction associated with said second selected region, said semiconductor substrate having first and second major surfaces, said memory cell circuit comprising: a memory cell including at least a field effect memory transistor comprising: said first selected region which intersects said first major surface, said second selected region which intersects said first major surfaces and which is spaced apart from said first selected region in said first major surface, and insulating means disposed on said first major surface with said insulating means having provided therewith a first gate conductive means, said first gate conductive means being located at least in part by that region of said first major surface which is between said first and second selected regions but with said first gate conductive means separated from said first major surface by said insulating means; and associated memory cell means associated with said memory cell including: a voltage setting means which, in response to a writing signal, selectively impresses between said first selected region and first conductivity portions of said semiconductor substrate a cell writing voltage of a value to reverse bias said first semiconductor junction, but where also said cell writing voltage is of a value insufficient to cause significant accumulation of charge on said first gate conductive means if solely impressas aforesaid while, concurrently, any significant current is prevented from flowing through said second selected region; and a voltage setting active device formed at least in part in said substrate which, in response to a select signal being provided thereto to indicate in conjunction with said writing signal that said memory cell has been selected, selectively places said second selected region at a voltage value to effectively forward bias said second semiconductor junction sufficiently to allow charge to accumulate in said first gate conductive means to an extent permitting said field effect memory transistor to be in an "on" condition when said cell writing voltage is concurrently impressed as aforesaid, said voltage setting active device being capable of selectively placing said second selected region at a voltage value as a foresaid when said select signal has a magnitude substantially smaller than that of said writing signal, and said voltage setting active device, in response to said select signal provided thereto indicating said memory cell has not been selected, places said second selected region at a voltage value which provides a reverse bias on said second semiconductor junction.