Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
129 words
A system for providing output pulses of a predetermined width after a predetermined delay from the receipt of a pretrigger pulse including a non-retriggerable, main delay one-shot for receiving said pretrigger pulse and having a predetermined timing cycle for providing said predetermined delay, and further comprising: a first trailing edge discriminator connected to the output of said main delay one-shot; auxiliary delay means operably coupled to said main delay one-shot for responding to pretrigger pulses occurring during said main delay one-shot timing cycle when said predetermined delay is greater than said predetermined width; and a retriggerable pulse width one-shot connected to the output of said auxiliary delay means and operably coupled to the output of said first trailing edge discriminator for providing said output pulses of a predetermined width.
Claim 2
Independent Claim
129 words
A system for providing output pulses of a predetermined width after a predetermined delay from the receipt of a pretrigger pulse including a non-retriggerable, main delay one-shot for receiving said pretrigger pulse and having a predetermined timing cycle for providing said predetermined delay, and further comprising: a first trailing edge discriminator connected to the output of said main delay one-shot; auxiliary delay means operably coupled to said main delay one-shot for responding to pretrigger pulses occurring during said main delay one-shot timing cycle when said predetermined delay is greater than said predetermined width; and a retriggerable pulse width one-shot connected to the output of said auxiliary delay means and operably coupled to the output of said first trailing edge discriminator for providing said output pulses of a predetermined width.
Claim 3
Dependent Claim
108 words
The system of claim 1 in which said auxiliary delay means comprises: an AND gate having a first input connected to the input of said main delay one-shot and a second input connected to the output of said main delay one-shot; an auxiliary delay one-shot connected to the output of said AND gate; a trailing edge discriminator connected to the output of said auxiliary delay one-shot; and an OR gate having a first input connected to the output of said first trailing edge discriminator, a second input connected to the output of said second trailing edge discriminator and having its output connected to said retriggerable pulse width one-shot.
Claim 4
Dependent Claim
23 words
The system of claim 2 including a dual constant current source connected to both said main delay one-shot and said auxiliary delay one-shot.
Claim 5
Dependent Claim
33 words
The system of claim 3 wherein said dual constant current source includes control means for simultaneously controlling the pulse widths of the pulses generated by both said main delay and auxiliary delay one-shots.
Claim 6
Dependent Claim
151 words
The system of claim 3 wherein said main delay one-shot and said auxiliary delay one-shot include a main delay R-C timing circuit and an auxiliary delay R-C timing circuit respectively; said main delay R-C timing circuit including a first resistor, first means for reducing the recovery time of said main delay one-shot without affecting the quasistable period thereof, said first means having a first terminal connected to said first resistor, said main delay R-C timing circuit further including a first capacitor connected to a second terminal of said first means; and said auxiliary delay R-C timing circuit including a second resistor, second means for reducing the recovery time of said auxiliary delay one-shot without affecting the quasistable period thereof, said second means having a first terminal connected to said second resistor, said auxiliary delay R-C timing circuit further including a second capacitor connected to a second terminal of said second means.
Claim 7
Dependent Claim
57 words
The system of claim 5 wherein said first means comprises first and second transistors each having a base connected to said first resistor and an emitter connected to said first capacitor; and said second means comprises third and fourth transistors each having a base connected to said second resistor and an emitter connected to said second capacitor.
Claim 8
Dependent Claim
23 words
The system of claim 6 wherein said first and third transistors are NPN transistors and said second and fourth transistors are PNP transistors.