Abstract Each processor in the system is provided with a processor bus over which access to all storage and peripheral equipments is gained. Each access is performed as an address read or write operation. However, under certain circumstances it is necessary to perform a "read-and-hold" operation when accessing a data word which is to be modified. Typically, entries in the master capability table fall into such a category where the data word, while being modified, must not be accessed by any other processor. In such a read-and-hold operation it is vital that the store accessed is held throughout the period of the read-and-hold operation. This facility is obtained by incorporating parity inverting arrangements in each access unit and each processor so that the parity for a read-and-hold operation is inverted. A failure of the hold facility would be detected by the interrogating processor since a parity failure would be observed at the end of the operation. The detection of parity failure causes the automatic entry into fault-interrupt arrangements.
A data processing system comprising in combination (i) a plurality of processing modules, each of said processing modules having means for initiating read, write, or read-and-hold operations, (ii) a common memory having a plurality of storage modules, (iii) individual highway busses for connecting each processing module to all storage modules for read, write or read-and-hold storage module access operations, (iv) means for generating, in each storage module, a parity indication indicative of the address of the storage location accessed by a processing module which indication is returned by way of the connecting highway bus to the accessing module in response to a storage module access operation and means for inverting in each storage module the parity indication returned during a write operation which follows immediately after a read-and-hold operation, (v) means for generating, in each processing module, the expected parity indication and (vi) means for comparing, in each processing module, the expected parity indication with the returned parity indication and for initiating a fault condition if the two parity indications are different.
Claim 2
Dependent Claim
172 words
A data processing system comprising in combination (i) a plurality of processing modules, each of said processing modules having means for initiating read, write, or read-and-hold operations, (ii) a common memory having a plurality of storage modules, (iii) individual highway busses for connecting each processing module to all storage modules for read, write or read-and-hold storage module access operations, (iv) means for generating, in each storage module, a parity indication indicative of the address of the storage location accessed by a processing module which indication is returned by way of the connecting highway bus to the accessing module in response to a storage module access operation and means for inverting in each storage module the parity indication returned during a write operation which follows immediately after a read-and-hold operation, (v) means for generating, in each processing module, the expected parity indication and (vi) means for comparing, in each processing module, the expected parity indication with the returned parity indication and for initiating a fault condition if the two parity indications are different.
Claim 3
Dependent Claim
66 words
A data processing system according to claim 1 in which each storage module has an associated access unit which includes a bistable device which is conditioned to a first state when a read-and-hold operation occurs and is conditioned to a second state when a write operation occurs after a read-and-hold operation, to enable the inverse parity indication to be returned to the particular data processing module.