Patent US4047290A successfully refreshed from Google Patents.
US4047290A
Expired / Lapsed
US
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Process for the production of a multi-chip wiring arrangement
Assignee: Siemens AG
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Filing: 1975-09-02
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Granted: 1977-09-13
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Expires: 1995-09-02
Abstract
Abstract A process for producing multi-chip wiring arrangements which consist of a ceramic carrier with through contact holes associated with thin film wiring on one side of the carrier and with multi layer, thick layer wiring on the other side of the carrier. The holes on the one side of the carrier are metallized and galvanically strengthened while the holes on the other side of the carrier are sealed by baking therein a thick layer of paste. Thereafter the multi layer, thick layer wiring and the thin film wiring are produced in that order.
Inventors
- 👤 Artur Weitze
- 👤 Michail Sapunarow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:30
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/111; H05K1/112; H05K1/114; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3452; H05K3/40; H05K3/4038; H05K3/4053; H05K3/4061; H05K3/42; H05K3/425; H05K3/426; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W70/685; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0347; H05K2201/20; H05K2201/2081; H05K2203/00; H05K2203/05; H05K2203/0502; H05K2203/0542; H05K2203/07; H05K2203/0703; H05K2203/0723; H05K3/10; H05K3/108; H05K3/22; H05K3/24; H05K3/245; H05K3/246; H05K3/38; H05K3/388; H05K3/46; H05K3/4602; H05K3/4605; H05K3/4644; H05K3/4664; H05K3/4667; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
88 words
A method for producing a multi-chip wiring arrangement on a carrier comprising the steps of: forming through holes in the carrier, metallizing and galvanically strengthening the walls and edge zones of the holes on one side of the carrier, filling the holes on the other side of the carrier with a conductive paste, baking the conductive paste in the holes and thereby sealing the same, forming multi-thick layer wiring on the other side of the carrier and forming thin film wiring on said one side of the carrier.
Claim 2
Independent Claim
88 words
A method for producing a multi-chip wiring arrangement on a carrier comprising the steps of: forming through holes in the carrier, metallizing and galvanically strengthening the walls and edge zones of the holes on one side of the carrier, filling the holes on the other side of the carrier with a conductive paste, baking the conductive paste in the holes and thereby sealing the same, forming multi-thick layer wiring on the other side of the carrier and forming thin film wiring on said one side of the carrier.
Claim 3
Dependent Claim
31 words
A method in accordance with claim 1 wherein the carrier is a ceramic carrier and wherein the holes at said other side thereof are filled with a thick layer gold paste.
Claim 4
Dependent Claim
81 words
A method in accordance with claim 1 wherein the metallizing and galvanically strengthening of the walls and edge zones of the holes includes the steps of: forming an adhesive layer on the carrier and into said holes, forming a contacting layer on the carrier and into said holes, galvanically reinforcing said contacting layer in the region of the walls and edge zones of the holes, and etching away those areas of the adhesive and contacting layer which are not galvanically reinforced.
Claim 5
Dependent Claim
27 words
A method in accordance with claim 3 wherein the adhesive layer is formed from titanium and the contacting layer and the galvanic reinforcement consist of gold layers.
Claim 6
Dependent Claim
89 words
A method in accordance with claim 1 the forming of the thin film wiring includes the steps of: depositing a base layer on the carrier, depositing a contacting layer on said base layer, galvanically depositing a conductive layer onto the contacting layer; an intermediate layer onto said conductive layer; and a solder-rejecting layer on areas of the conductive layer excluding the connection surfaces, etching away exposed areas of the base layer and contacting layer, and covering the connection surfaces with a solderable contact layer by selective currentless metal deposition.
Claim 7
Dependent Claim
40 words
A method in accordance with claim 5 wherein the base layer is titanium, the contact layer is copper, the conductive layer is copper, the intermediate layer is nickel, the solder-rejecting layer is chrome and the solderable contact layer is gold.
References Cited (Backward Citations)
US3756891A
Cited
US3672986A
Cited
US3773554A
Cited
US3619725A
Cited
US3808046A
Cited
US3808681A
Cited
US3808049A
Cited
US3934336A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-12 | 1981-03-14 | 1981-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-12 | 1985-03-14 | 1985-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-12 | 1989-03-14 | 1989-09-13 | $7700.00 | Window Closed / Lapsed |