Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
239 words
A storage arrangement for use as an associative memory, comprising: a main memory for storing data composed of an associative component and a non-associative component; a comparator device connected to said main memory to compare the associative part of data therefrom with a search word; said main memory comprising a linearly addressed storage bank divided into a pages each including b rows, each of said rows including a storage position for the data and a portion for storing reference characteristics; page and row address converters for providing page and row addresses in response to receipt of a prefix; an extension counter connected to said page address converter to co-determine page address in accordance with its relavant count and whose count is increased by one when an initially addressed storage position is engaged; a book-keeping memory connected to said page address converters and operated to be read row-by-row, said book-keeping memory comprising a rows each including b bit positions, where each row corresponds to a page and each bit position corresponds to a row of said main memory, each bit position storing a mark indicating seizure of the corresponding row of said main memory; and a book-keeping control unit connected to said counter, to said row address converters, to said book-keeping memory and to said main memory, and operable to control the setting and interrogation of the seizure marks and the selection of equivalent storage positions in said main memory.
Claim 2
Dependent Claim
239 words
A storage arrangement for use as an associative memory, comprising: a main memory for storing data composed of an associative component and a non-associative component; a comparator device connected to said main memory to compare the associative part of data therefrom with a search word; said main memory comprising a linearly addressed storage bank divided into a pages each including b rows, each of said rows including a storage position for the data and a portion for storing reference characteristics; page and row address converters for providing page and row addresses in response to receipt of a prefix; an extension counter connected to said page address converter to co-determine page address in accordance with its relavant count and whose count is increased by one when an initially addressed storage position is engaged; a book-keeping memory connected to said page address converters and operated to be read row-by-row, said book-keeping memory comprising a rows each including b bit positions, where each row corresponds to a page and each bit position corresponds to a row of said main memory, each bit position storing a mark indicating seizure of the corresponding row of said main memory; and a book-keeping control unit connected to said counter, to said row address converters, to said book-keeping memory and to said main memory, and operable to control the setting and interrogation of the seizure marks and the selection of equivalent storage positions in said main memory.
Claim 3
Dependent Claim
63 words
The storage arrangement of claim 1, wherein said book-keeping control unit includes means responsive to an extension counter count EZ, where |EZ|> φ, to prevent selection of a storage position in said main memory by a row formed from the prefix and assign a free storage position in said main memory for a new entry as determined by interrogation of said book-keeping memory.
Claim 4
Dependent Claim
35 words
The storage arrangement of claim 2, wherein said book-keeping control unit comprises a priority network operable to cause storage of new entries in a free row with the highest particular priority within an addressed page.
Claim 5
Dependent Claim
151 words
The storage arrangement of claim 3, wherein said page address converter comprises recoding means for recoding received data in dependence on the lower-value bits of the contents of said extension counter, said row address converter includes means for receiving and translating the number n of lower-value bits of a bit combination, which is equal to the number n of the bits of a row address, for input to said book-keeping control unit, the number m of higher-value bits of a bit combination, equal to the number m of the bits of a page address recoded by said recoding means while preserving the bit number m, and comprising an adder connected to said extension counter and to said page address converter for adding the higher-value bits of the contents of said extension counter to the bits supplied by said page address converter in modulo 2 m fashion to provide a page address.
Claim 6
Dependent Claim
15 words
The storage arrangement of claim 4, wherein said recoding means comprises a logic linking network.
Claim 7
Dependent Claim
15 words
The storage arrangement of claim 4, wherein said recoding means comprises a read only memory.
Claim 8
Dependent Claim
77 words
The storage arrangement of claim 4, comprising a bit mixer to acyclically exchange the positions of k bits of an extended prefix, where k is a whole-number multiple of the bits n + m of a page and row address, and a reduction converter having means for reducing the k bits to n + m bits, said page address converter connected to receive the m bits and said row address converter connected to receive the n bits.
Claim 9
Dependent Claim
15 words
The storage arrangement of claim 7, wherein said reduction converter comprises a read only memory.
Claim 10
Dependent Claim
15 words
The storage arrangement of claim 7, wherein said reduction converter comprises a logic linking network.
Claim 11
Dependent Claim
46 words
The storage arrangement of claim 9, wherein said logic linking network comprises a plurality of exclusive-or gates arranged in the first and second groups with the outputs of two gates of the first group connected to the inputs of a single gate of the second group.
Claim 12
Dependent Claim
59 words
The storage arrangement of claim 4, for storing association words having an alpha-numeric coding, comprising a code compressor connected in series with said page and address converters to gate out unused code combinations and eliminate redundant, where the number of the bits fed to said code compressor exceeds the number n + m by the number of redundant bits.