Patent US4045815A successfully refreshed from Google Patents.
US4045815A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for combining analog and image signals into a standard video format
Assignee: United States Department of Health and Human Services
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Filing: 1976-02-04
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Granted: 1977-08-30
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Expires: 1996-02-04
Abstract
Abstract A system for combining at least one analog signal, such as EKG signal, and an image signal, such as video signal representing a fluoroscopic view of a patient's heart or the like. The system includes a summing amplifier, which provides an input to a TV monitor and/or video recorder. The first input to the summing amplifier is provided from a TV camera arranged to view a physiological activity. A second input to the summing amplifier is provided from an encoder which receives one analog signal representing physiological data. The encoder includes an analog-to-digital (A/D) converter which receives the analog signal and feeds it to a random access memory (RAM). The A/D converter and the RAM are controlled by sync signals derived from a master camera control unit, which also provides sync signals to the TV camera.
Inventors
- 👤 James M. Griffith
- 👤 Walter L. Henry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:46
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/08; A; A61; A61B; A61B5/00; A61B5/24; A61B5/316; A61B5/318; A61B5/346; A61B5/349; A61B5/352; H04N5/00; H04N5/222; H04N5/262; H04N5/278
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
450 words
A system for combining at least one analog signal with video signals comprising: an analog-to-digital converter having an analog signal input means and an enabling signal input means; a random access memory having a data input means coupled to said analog-to-digital for receiving its digital output, said random access memory having a write input means, a row address input means and a column address input means; a controlled gate circuit means having its data signal input means coupled to said random access memory for receiving its output, said gate circuit means having a control signal input means; a source of vertical and horizontal sync signals; first multivibrator means, second multivibrator means and third multivibrator means; means coupling vertical sync signals from said source to said enabling signal input means of said analog-to-digital converter for enabling same upon occurrence of each vertical sync signal; means coupling vertical sync signals from said source to an input of said first multivibrator means, said write input means of said random access memory being coupled to said first multivibrator means; a first counter means having an enable input means, a clock input means and a reset input means, means for coupling vertical sync signals from said source to said reset input of said first counter means, means for coupling horizontal sync signals from said source to said clock input means of said first counter means, and means for coupling said enable input means of said first counter means to an output of said second multivibrator means, said second multivibrator means having its input means coupled to said source for receiving horizontal sync signals therefrom, and said row address input means of said random access memory being coupled to said first counter means for receiving its output signals; oscillator means; a second counter means having a clock input means coupled to said oscillator means for receiving output signals therefrom and having reset input means coupled to said third multivibrator means for receiving output signals therefrom, said third multivibrator means having its input means coupled to said source for receiving vertical sync signals therefrom, and said column address input means of said random access memory being coupled to said second counter means for receiving its output signals; logic circuit means having a first input coupled to said third multivibrator means for receiving its output signals and having a second input coupled to said second multivibrator means for receiving its output signals, said logic circuit having its output coupled to said control signal input means of said gate circuit means for enabling said gate circuit; an additional source supplying video signals; and means coupled to said additional source and to said gate circuit means for combining signals therefrom.
Claim 2
Independent Claim
450 words
A system for combining at least one analog signal with video signals comprising: an analog-to-digital converter having an analog signal input means and an enabling signal input means; a random access memory having a data input means coupled to said analog-to-digital for receiving its digital output, said random access memory having a write input means, a row address input means and a column address input means; a controlled gate circuit means having its data signal input means coupled to said random access memory for receiving its output, said gate circuit means having a control signal input means; a source of vertical and horizontal sync signals; first multivibrator means, second multivibrator means and third multivibrator means; means coupling vertical sync signals from said source to said enabling signal input means of said analog-to-digital converter for enabling same upon occurrence of each vertical sync signal; means coupling vertical sync signals from said source to an input of said first multivibrator means, said write input means of said random access memory being coupled to said first multivibrator means; a first counter means having an enable input means, a clock input means and a reset input means, means for coupling vertical sync signals from said source to said reset input of said first counter means, means for coupling horizontal sync signals from said source to said clock input means of said first counter means, and means for coupling said enable input means of said first counter means to an output of said second multivibrator means, said second multivibrator means having its input means coupled to said source for receiving horizontal sync signals therefrom, and said row address input means of said random access memory being coupled to said first counter means for receiving its output signals; oscillator means; a second counter means having a clock input means coupled to said oscillator means for receiving output signals therefrom and having reset input means coupled to said third multivibrator means for receiving output signals therefrom, said third multivibrator means having its input means coupled to said source for receiving vertical sync signals therefrom, and said column address input means of said random access memory being coupled to said second counter means for receiving its output signals; logic circuit means having a first input coupled to said third multivibrator means for receiving its output signals and having a second input coupled to said second multivibrator means for receiving its output signals, said logic circuit having its output coupled to said control signal input means of said gate circuit means for enabling said gate circuit; an additional source supplying video signals; and means coupled to said additional source and to said gate circuit means for combining signals therefrom.
Claim 3
Dependent Claim
25 words
A system according to claim 1, further comprising monitor means coupled to said summing means and responsive to its output for displaying the composite video.
Claim 4
Dependent Claim
17 words
A system according to claim 1, wherein said additional source of video signals comprises a TV camera.
Claim 5
Dependent Claim
26 words
A system according to claim 1, including a source of said one analog signal, said source of analog signal being means responsive to a physiological activity.
Claim 6
Dependent Claim
22 words
A system according to claim 1, wherein said source of said one analog signal is a source of an analog EKG signal.
Claim 7
Dependent Claim
16 words
A system according to claim 1, wherein said logic circuit means consists of an AND circuit.
Claim 8
Dependent Claim
35 words
A system according to claim 1, wherein said first multivibrator means consists of two one-shot multivibrators coupled in series between said write input means of said random access memory and said source of sync signals.
Claim 9
Dependent Claim
33 words
A system according to claim 1, wherein said third multivibrator consists of two one-shot multivibrators coupled in series between said first input of said logic circuit means and said source of sync signals.
Claim 10
Dependent Claim
24 words
A system according to claim 1, wherein said first, second and third multivibrator means consist respectively of respective pairs of series connected one-shot multivibrators.
Claim 11
Dependent Claim
35 words
A system according to claim 1, wherein said second multivibrator means consists of two one-shot multivibrators coupled in series between said enable input means of said first counter means and said source of sync signals.
Claim 12
Dependent Claim
35 words
A system according to claim 10, wherein said third multivibrator means consists of two additional one-shot multivibrators coupled in series between said first input of said logic circuit means and said source of sync signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |