Complementary field effect transistor amplifier

Claim 2

In combination: first and second field effect transistors having conduction channels of opposite conductivity types connected in series between two circuit nodes, each transistor having source, gate and drain electrodes; said two source electrodes being connected to said two nodes, respectively and said two drain electrodes being connected to one another; a circuit input terminal coupled to said gate electrodes of said first and second transistors for applying an input signal thereto; a circuit output terminal coupled to said drain electrodes of said first and second transistors for providing an output signal; current controlled current source means for continuously supplying a first output current to said source electrode of said first transistor and controlling the value of said first output current in accordance with a first input current, and for continuously withdrawing a second output current from said source electrode of said second transistor and controlling the value of said second output current in accordance with a second input current; and circuit means for supplying said first and second input currents to said current controlled current source means and for controlling the ratio thereof in response to said input signal applied to said input terminal.

Claim 3

The combination recited in claim 1 further comprising first and second terminals for receiving an operating voltage thereacross and wherein said current controlled current source means comprises: first and second current mirror amplifiers, each having an input terminal, an output terminal and a sum terminal, said sum terminal being connected, respectively, to said first terminal and to said second terminal, said output terminals being connected, respectively, to said source electrode of said first transistor and to said source electrode of said second transistor, the input terminal of the first for receiving said first input current and the input terminal of the second for receiving said second input current.

Claim 4

The combination recited in claim 2 wherein said circuit means comprises: a first direct current conductive impedance element connected between said circuit input terminal and said first current mirror amplifier input terminal; and a second direct current impedance element connected between said circuit input terminal and said second current mirror amplifier input terminal.

Claim 5

The combination recited in claim 2 wherein said circuit means comprises: a third field effect transistor having a conduction channel of the same conductivity type as said first field effect transistor, having a source electrode connected to said first current mirror amplifier input terminal, having a drain electrode connected to said second terminal and having a gate electrode connected to said circuit input terminal; and a fourth field effect transistor having a conduction channel of the same conductivity type as said second transistor, having a source electrode connected to said second current mirror amplifier input terminal, having a drain electrode connected to said first terminal and having a gate electrode connected to said circuit input terminal.

Claim 6

The combination recited in claim 2 wherein said circuit means comprises: a third field effect transistor having a conduction channel of the same conductivity type as said first field effect transistor, having a source electrode connected to said first current mirror amplifier input terminal, and having a drain and a gate electrode, each connected to said circuit input terminal; and a fourth field effect transistor having a conduction channel of the same conductivity type as said second field effect transistor, having a source electrode connected to said second current mirror amplifier input terminal and having a drain and a gate electrode, each connected to said circuit input terminal.

Claim 7

The combination receited in claim 2 wherein said first current mirror amplifier comprises third and fourth field effect transistor of the same channel conductivity type as said first field effect transistor and connected at the source electrodes thereof to said first current mirror amplifier sum terminal, the gate and drain electrodes of the fourth transistor and the gate electrode of the third transistor being connected to said first current mirror amplifier input terminal, the drain electrode of the third transistor being connected to said first current mirror amplifier output terminal; and wherein said second current mirror amplifier comprises fifth and sixth field effect transistors of the same channel conductivity type as said second field effect transistor and connected at the source electrodes thereof to said second current mirror amplifier sum terminal, the gate and drain electrodes of the sixth transistor and the gate electrode of the fifth transistor being connected to said second current mirror amplifier input terminal, the drain electrode of the fifth transistor being connected to said second current mirror amplifier output terminal.

Claim 8

An amplifier, comprising: first and second terminals for receiving an operating voltage therebetween; first and second complementary field effect transistors having the drain electrodes thereof connected to a circuit output terminal and the gate electrodes thereof connected to a circuit input terminal; a third field effect transistor of the same channel conductivity type as said first field effect transistor, the source and drain electrodes thereof being coupled, respectively to said first terminal and to the source electrode of said first transistor; first voltage regulating means coupled to the gate electrode of said third transistor for regulating the gate-to-source voltage thereof in accordance with a first input current; a fourth field effect transistor of the same channel conductivity type as said second field effect transistor, the source and drain electrodes thereof being coupled, respectively, to said second terminal and to the source electrode of said second transistor; second voltage regulating means coupled to the gate electrode of said fourth transistor for regulating the gate-to-source voltage thereof in accordance with a second input current; and input means for supplying said first and second input currents to said first and second voltage regulating means and for controlling the ratio thereof in response to an input signal applied to said circuit input terminal.

Claim 9

An amplifier, comprising: first and second terminals for receiving an operating voltage therebetween; first and second complementary field effect transistors having the drain electrodes thereof connected to a circuit output terminal and the gate electrodes thereof connected to a circuit input terminal; a third field effect transistor of the same channel conductivity type as said first field effect transistor, the source and drain electrodes thereof being coupled, respectively to said first terminal and to the source electrode of said first transistor; first voltage regulating means coupled to the gate electrode of said third transistor for regulating the gate-to-source voltage thereof in accordance with a first input current; a fourth field effect transistor of the same channel conductivity type as said second field effect transistor, the source and drain electrodes thereof being coupled, respectively, to said second terminal and to the source electrode of said second transistor; second voltage regulating means coupled to the gate electrode of said fourth transistor for regulating the gate-to-source voltage thereof in accordance with a second input current; and input means for supplying said first and second input currents to said first and second voltage regulating means and for controlling the ratio thereof in response to an input signal applied to said circuit input terminal.

Claim 10

The amplifier recited in claim 7 wherein: said first regulator means comprises a fifth field effect transistor of the same channel conductivity type as said third field effect transistor, means coupling the source electrode of said fifth transistor to said first terminal, means coupling the gate and drain electrodes of said fifth transistor to the gate electrode of said third transistor and forming a first circuit node for receiving said first input current; and wherein said second regulator means comprises a sixth field effect transistor of the same channel conductivity type as said fourth field effect transistor, means coupling the source electrode of said sixth transistor to said second terminal, and means coupling the gate and drain electrodes of said sixth transistor to the gate electrode of said fourth transistor and forming a second circuit node for receiving said second input current.

Claim 11

The amplifier recited in claim 8 wherein said input means comprises: a seventh field effect transistor of the same channel conductivity type as said fifth field effect transistor, said seventh transistor being connected at the source electrode thereof to said first circuit node and at the gate electrode thereof to said circuit input terminal; an eighth field effect transistor of the same channel conductivity type as said sixth field effect transistor, said eighth transistor being connected at the source electrode thereof to said second circuit node and at the gate electrode thereof to said circuit input terminal; and means coupling the drain electrode of each of said seventh and eighth transistors to said circuit input terminal.

Claim 12

The amplifier recited in claim 8 wherein said input means comprises: a seventh field effect transistor of the same channel conductivity type as said fifth field effect transistor, said seventh transistor being connected at the source electrode thereof to said first circuit node and at the gate electrode thereof to said circuit input terminal; an eighth field effect transistor of the same channel conductivity type as said sixth field effect transistor, said eighth transistor being connected at the source electrode thereof to said second circuit node and at the gate electrode thereof to said circuit input terminal; means for applying a first reference voltage to the drain electrode of said seventh transistor; and means for applying a second reference voltage to the drain electrode of said eighth transistor.

Claim 13

The amplifier recited in claim 10 wherein said means for applying said first reference voltage to the drain electrode of said seventh transistor comprises means coupling the drain electrode thereof to said second terminal and wherein said means for applying said second reference voltage to the drain electrode of said eighth transistor comprises means coupling the drain electrode thereof to said first terminal.

Claim 14

An amplifier, comprising, in combination: an input terminal for receiving an input signal, an output terminal for providing an output signal and first and second supply terminals for receiving, respectively, first and second operating voltages; first and second field effect transistors of a first conductivity type, each having source, gate and drain electrodes, the gate and drain electrodes of the first transistor being connected respectively, to said input and output terminals, the source and drain electrodes of the second transistor being connected, respectively, to said first supply terminal and to the source electrode of said first transistor; third and fourth field effect transistors of a second conductivity type, each having source, gate and drain electrodes, the gate and drain electrodes of the third transistor being connected, respectively, to said input and output terminals, the source and drain electrodes of the fourth transistor being connected, respectively, to said second supply terminal and to the source electrode of said third transistor; first means connected to said input terminal and to at least the first of said supply terminals for applying a bias voltage across the gate and source of electrodes of said second transistor in proportion to but less than the potential difference appearing between said first terminal and said input terminal; and second means connected to said input terminal and to at least the second of said supply terminals for applying a bias voltage across the gate and source electrodes of said fourth transistor in proportion to but less than the potential difference appearing between said second terminal and said input terminal.

Claim 15

An amplifier, comprising, in combination: an input terminal for receiving an input signal, an output terminal for providing an output signal and first and second supply terminals for receiving, respectively, first and second operating voltages; first and second field effect transistors of a first conductivity type, each having source, gate and drain electrodes, the gate and drain electrodes of the first transistor being connected respectively, to said input and output terminals, the source and drain electrodes of the second transistor being connected, respectively, to said first supply terminal and to the source electrode of said first transistor; third and fourth field effect transistors of a second conductivity type, each having source, gate and drain electrodes, the gate and drain electrodes of the third transistor being connected, respectively, to said input and output terminals, the source and drain electrodes of the fourth transistor being connected, respectively, to said second supply terminal and to the source electrode of said third transistor; first means connected to said input terminal and to at least the first of said supply terminals for applying a bias voltage across the gate and source of electrodes of said second transistor in proportion to but less than the potential difference appearing between said first terminal and said input terminal; and second means connected to said input terminal and to at least the second of said supply terminals for applying a bias voltage across the gate and source electrodes of said fourth transistor in proportion to but less than the potential difference appearing between said second terminal and said input terminal.

Claim 16

The amplifier recited in claim 12 wherein said first means comprises a first impedance element connected between said first terminal and said gate electrode of said second transistor and a second impedance element connected between said input terminal and said gate electrode of said second transistor and wherein said second means comprises a third impedance element connected between said second terminal and said gate electrode of said fourth transistor and a fourth impedance element connected between said input terminal and said gate electrode of said fourth transistor.

Claim 17

The amplifier recited in claim 12 wherein said first means comprises fifth and sixth field effect transistors of said first conductivity type, each having source, gate and drain electrodes, the fifth transistor having the source electrode thereof coupled to said first terminal and the gate and drain electrodes thereof coupled to said gate electrode of said second transistor, the sixth transistor having the source electrode thereof coupled to said gate electrode of said second transistor and having the gate and drain electrodes thereof coupled to said input terminal; and wherein said second means comprises seventh and eighth field effect transistors of said second conductivity type, each having source, gate and drain electrodes, said seventh transistor having the source electrode thereof coupled to said second terminal and the gate and drain electrodes thereof coupled to said gate electrode of said fourth transistor, the eighth transistor having the source electrode therof coupled to said gate electrode of said fourth transistor and having the gate and drain electrodes thereof coupled to said input terminal.

Claim 18

The amplifier recited in claim 12 wherein said first means comprises fifth and sixth field effect transistors of said first conductivity type, each having source, gate and drain electrodes, the fifth transistor having the source electrode thereof coupled to said first terminal and the gate and drain electrodes thereof coupled to said gate electrode of said second transistor, the sixth transistor having the source electrode thereof coupled to said gate electrode of said second transistor and having the gate and drain electrodes thereof coupled, respectively, to said input terminal and said second terminal; and wherein said second means comprises seventh and eighth field effect transistors of said second conductivity type, each having source, gate and drain electrodes, said seventh transistor having the source electrode thereof coupled to said second terminal and the gate and drain electrodes thereof coupled to said gate electrode of said fourth transistor, the eighth transistor having the source electrode thereof coupled to said gate electrode of said fourth transistor and having the gate and drain electrodes thereof coupled, respectively, to said input terminal and said first terminal.

Claim 19

An amplifier, comprising: first and second field effect transistors of first and second conductivity types, respectively, each having source, gate and drain electrodes, said gate electrodes being connected to a signal input terminal, said drain electrodes being connected to a signal output terminal; first and second complementary current mirror amplifiers each having input, common output terminals, said common terminals for receiving an operating voltage thereacross, said output terminals being connected to respective ones of said source electrodes; and input means for supplying input currents to the input terminals of said current mirror amplifiers and for controlling the ratio thereof in accordance with an input signal applied to said input signal terminal.

Claim 20

An amplifier, comprising: first and second field effect transistors of first and second conductivity types, respectively, each having source, gate and drain electrodes, said gate electrodes being connected to a signal input terminal, said drain electrodes being connected to a signal output terminal; first and second complementary current mirror amplifiers each having input, common output terminals, said common terminals for receiving an operating voltage thereacross, said output terminals being connected to respective ones of said source electrodes; and input means for supplying input currents to the input terminals of said current mirror amplifiers and for controlling the ratio thereof in accordance with an input signal applied to said input signal terminal.

Claim 21

The amplifier recited in claim 16 wherein said input means comprises: a third field effect transistor of said first conductivity type having a source electrode connected to said input terminal of said first current mirror amplifier, a drain electrode connected to said common terminal of said second current mirror amplifier and a gate electrode connected to said signal input terminal; and a fourth field effect transistor of said second conductivity type having a source electrode connected to said input terminal of said second current mirror amplifier, a drain electrode connected to said common terminal of said first current mirror amplifier and a gate electrode connected to said signal input terminal.

Claim 22

The amplifier recited in claim 16 wherein said input means comprises: a third field effect transistor of said first conductivity type having a source electrode connected to said input terminal of said first current mirror amplifier and having a drain electrode and a gate electrode, said drain and gate electrodes being connected to said signal input terminal; and a fourth field effect transistor of said second conductivity type having a source electrode connected to said input terminal of said second current mirror amplifier and having a gate electrode and a drain electrode, said gate and drain electrodes being connected to said signal input terminal.