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US4045691A Expired / Lapsed US ⏱️ 0.0 years remaining

Level shift circuit

Assignee: Seiko Instruments Inc
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Filing: 1976-09-21
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Granted: 1977-08-30
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Expires: 1996-09-21
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Abstract

Abstract A level shift circuit comprises an inverter connected to a first voltage supply source and supplied with an input pulse. A condenser and a directional switching element are connected in series between the output point of the inverter and one potential point of the first voltage supply source. The input of a first MOS-FET is connected to the output of the inverter while the input of a second MOS-FET is connected to a connection point between the condenser and the directional switching element. The source of the first MOS-FET is connected to a common terminal of first and second voltage supply sources while the source of the second MOS-FET is connected to the other terminal of the second voltage supply source. An output voltage is generated between a common connecting point of the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.

Inventors

  • 👤 Kazuhiro Asano

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 10:35
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 133 words
A level shift circuit comprising an inverter, means for supplying a first voltage to said inverter, means for applying an input pulse to said inverter, a condenser, a directional switching element, and first and second MOS-FETs, means connecting an output of said inverter to one terminal of said condenser and to the gate of said first MOS-FET, means connecting a second terminal of said condenser to the gate of said second MOS-FET and through said directional switching element to one terminal of said first voltage supply means, means connecting the source of said first MOS-FET to the other terminal of said first voltage supply means, means connecting the source of said second MOS-FET to a second voltage supply means, and means connecting the drains of both of said MOS-FETs to an output terminal.
Claim 2
Dependent Claim 133 words
A level shift circuit comprising an inverter, means for supplying a first voltage to said inverter, means for applying an input pulse to said inverter, a condenser, a directional switching element, and first and second MOS-FETs, means connecting an output of said inverter to one terminal of said condenser and to the gate of said first MOS-FET, means connecting a second terminal of said condenser to the gate of said second MOS-FET and through said directional switching element to one terminal of said first voltage supply means, means connecting the source of said first MOS-FET to the other terminal of said first voltage supply means, means connecting the source of said second MOS-FET to a second voltage supply means, and means connecting the drains of both of said MOS-FETs to an output terminal.
Claim 3
Dependent Claim 92 words
A level shift circuit according to claim 1, in which said inverter comprises a P type MOS-FET and an N type MOS-FET, said input pulse being applied to the gates of both of said MOS-FETs of said inverter, the source of said N type MOS-FET being connected to said one terminal of said first voltage supply means, the source of said P type MOS-FET being connected to said other terminal of said first voltage supply means and the drains of said MOS-FETs being connected together and comprising the output of said inverter.
Claim 4
Dependent Claim 29 words
A level shift circuit according to claim 1, in which said directional switching element comprises a diode the anode of which is connected to one terminal of said condenser.
Claim 5
Dependent Claim 45 words
A level shift circuit according to claim 1, in which said directional switching element comprises an N type MOS-FET having its gate and source connected to one terminal of said condenser and its drain connected to said one terminal of said first voltage supply means.

References Cited (Backward Citations)

US3675144A Cited
US3842411A Cited
US3916430A Cited
US3900746A Cited
US4000412A Cited
US4006491A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-08-29 1981-02-28 1981-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-08-29 1985-02-28 1985-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-08-29 1989-02-28 1989-08-30 $7700.00 Window Closed / Lapsed

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