Patent US4045685A successfully refreshed from Google Patents.
US4045685A
Expired / Lapsed
US
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Mos power stage for generating non-overlapping two-phase clock signals
Assignee: ITT Inc
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Filing: 1976-10-29
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Granted: 1977-08-30
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Expires: 1996-10-29
Abstract
Abstract This relates to an MOS power stage of a two-phase clock signal generator arranged on the same integrated circuit chip as the circuit to be driven. The generator consists of one MOSFET inverter, the output of which is multiplexed by the two clock signals. In this manner, power loss in the MOSFET is reduced.
Inventors
- 👤 Wilfried W. Gehrig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
134 words
An MOS-power stage for generating non-overlapping two-phase clock signals from a first square wave signal having a pulse duty factor less than 0.5, comprising: a power inverter coupled to said square wave signals; first and second transistors each having a main current path coupled to the output of said power inverter; first and second capacitors, said first transistor having a gate coupled to its main current path via said first capacitor, and said second transistor having a gate coupled to its main current path via said second capacitor; and means for coupling the gate terminals of said first and second transistors to one of two inversely related auxiliary square wave signals, each having a pulse duty factor of 0.5 and a frequency equal to substantially half the frequency of said first square wave signal.
Claim 2
Dependent Claim
134 words
An MOS-power stage for generating non-overlapping two-phase clock signals from a first square wave signal having a pulse duty factor less than 0.5, comprising: a power inverter coupled to said square wave signals; first and second transistors each having a main current path coupled to the output of said power inverter; first and second capacitors, said first transistor having a gate coupled to its main current path via said first capacitor, and said second transistor having a gate coupled to its main current path via said second capacitor; and means for coupling the gate terminals of said first and second transistors to one of two inversely related auxiliary square wave signals, each having a pulse duty factor of 0.5 and a frequency equal to substantially half the frequency of said first square wave signal.
Claim 3
Dependent Claim
27 words
An MOS-power stage according to claim 1 wherein said auxiliary square wave signals are produced by a frequency divider stage coupled to said first square wave signal.
Claim 4
Dependent Claim
15 words
An MOS-power stage according to claim 2 wherein said frequency divider is a binary flip-flop.
Claim 5
Dependent Claim
39 words
An MOS-power stage according to claim 2 wherein said inverter comprises: a third transistor having a gate coupled to said first square wave signal; and a resistor coupled in series with the main current path of said third transistor.
Claim 6
Dependent Claim
25 words
An MOS-power stage according to claim 2 wherein said first square wave signal and said auxiliary square wave signals are generated by a Johnson counter.
Claim 7
Dependent Claim
116 words
An MOS-power stage according to claim 5 wherein said Johnson counter is a four-stage counter further including: a first AND-gate having inputs coupled to the third and fourth stage of said counter; a second AND-gate having inputs coupled to the third and fourth stages of said counter; a NOR-gate having inputs coupled to the outputs of said first and second AND-gates and an output for providing said first square wave signal; and first and second inverter stages, said first inverter stage coupled to the forth stage of said counter and said second inverter stage coupled to the third stage of said counter, the outputs of said first and second inverters providing said auxiliary square wave signals.
References Cited (Backward Citations)
US3479603A
Cited
US3536936A
Cited
US3641366A
Cited
US3777184A
Cited
US3805167A
Cited
US3986046A
Cited
US3870962A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |