Patent US4044452A successfully refreshed from Google Patents.
US4044452A
Expired / Lapsed
US
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Process for making field effect and bipolar transistors on the same semiconductor chip
Assignee: International Business Machines Corp
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Filing: 1976-10-06
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Granted: 1977-08-30
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Expires: 1996-10-06
Abstract
Abstract A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.
Inventors
- 👤 Shakir Ahmed Abbas
- 👤 Robert Charles Dockerty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:15
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10P30/21; H10P30/212; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0124; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10W15/00; H10W15/01; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/085; Y10S148/117
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
169 words
Method for manufacturing an integrated circuit structure having dielectrically isolated regions containing bipolar and field effect transistor devices comprising: providing a silicon monocrystalline substrate; etching said silicon in the areas to be the dielectric regions isolating the said field effect transistor devices; oxidizing the exposed silicon in said regions to form first oxidized areas; etching said silicon in the areas to be the dielectric regions isolating the said bipolar devices to form a mesa in the center of the etched area; oxidizing the exposed silicon areas to form a screen oxide area; ion implanting impurities through said screen oxide areas to form the subcollector for a bipolar device; growing thick silicon dioxide in said screen oxide areas to completely fill the areas with silicon dioxide and complete said dielectrically isolated regions; simultaneously forming the source, drain and emitter regions of said devices; forming gate insulator and gate electrodes for said field effect transistor devices; forming electrical contacts to said source, drain, gate, emitter, base and, collector of said devices.
Claim 2
Dependent Claim
169 words
Method for manufacturing an integrated circuit structure having dielectrically isolated regions containing bipolar and field effect transistor devices comprising: providing a silicon monocrystalline substrate; etching said silicon in the areas to be the dielectric regions isolating the said field effect transistor devices; oxidizing the exposed silicon in said regions to form first oxidized areas; etching said silicon in the areas to be the dielectric regions isolating the said bipolar devices to form a mesa in the center of the etched area; oxidizing the exposed silicon areas to form a screen oxide area; ion implanting impurities through said screen oxide areas to form the subcollector for a bipolar device; growing thick silicon dioxide in said screen oxide areas to completely fill the areas with silicon dioxide and complete said dielectrically isolated regions; simultaneously forming the source, drain and emitter regions of said devices; forming gate insulator and gate electrodes for said field effect transistor devices; forming electrical contacts to said source, drain, gate, emitter, base and, collector of said devices.
Claim 3
Dependent Claim
39 words
The method of claim 1 wherein, after formation of the source, drain and emitter regions a layer of insulating material is deposited over the source and drain regions of the field effect transistor to form an insulating layer therefor.
Claim 4
Dependent Claim
40 words
A method of claim 1 wherein, a semiconductor chip has a resistivity of about 2 ohms-centimeter and source, drain and emitter regions are formed by diffusion of an impurity material resulting in a dopant concentration of about 10 20 atoms/cc.
Claim 5
Dependent Claim
36 words
The method of claim 1 wherein, prior to formation of said emitter region, an impurity material is diffused into the region selected to be the base of the bipolar transistor to lower the base resistivity thereof.
Claim 6
Dependent Claim
21 words
The method of claim 1 wherein, said semiconductor chip is of P material and said source and drain are N+ diffusions.
Claim 7
Dependent Claim
21 words
The method of claim 1 wherein, the semiconductor chip is of P material and the bipolar transistor is an NPN device.
Claim 8
Dependent Claim
28 words
The method of claim 1 wherein the step of etching silicon in the areas to be dielectric regions isolating the bipolar transistor is effected by reactive ion etching.
References Cited (Backward Citations)
US3955269A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |