Patent US4044202A successfully refreshed from Google Patents.
US4044202A
Expired / Lapsed
US
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Plural frequency signalling systems
Assignee: The General Electric Company PLC
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Filing: 1975-12-29
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Granted: 1977-08-23
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Expires: 1995-12-29
Abstract
Abstract A receiver for use in a signalling system of the kind in which data is conveyed by transmitting a signal having alternately first and second frequencies. The receiver has circuitry for providing in response to the received signal two trains of pulses with frequencies corresponding to that of the received signal. The trains of pulses are fed to delay and coincidence detecting circuits which are so arranged that a first coincidence gate circuit produces an output only when the received signal has its first frequency and a second coincidence gate circuit produces an output only when the received signal has its second frequency.
Inventors
- 👤 Eugeniusz Antoszewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:19
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1563
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
201 words
A receiver for use in a signalling system of the kind wherein data is conveyed by transmitting a signal having alternately first and second frequencies comprising: shaping and squaring circuitry which provides in response to the received signal first and second trains of pulses, the two trains having frequencies correspondingly dependent on the frequency of the received signal and the durations of the pulses in each being independent of the durations of the pulses in the other train and small compared with the period of the received signal; a first delay circuit fed with one of said trains of pulses; a second delay circuit fed with one of said trains of pulses; a first coincidence gate circuit having as inputs the output of the first delay circuit and said first train of pulses; and a second coincidence gate circuit having as inputs the output of said second delay circuit and said second train of pulses; the delays of the delay circuits being such that the first coincidence gate circuit produces an output substantially only when the received signal has its first frequency; and the second coincidence gate circuit produces an output substantially only when the received signal has its second frequency.
Claim 2
Dependent Claim
201 words
A receiver for use in a signalling system of the kind wherein data is conveyed by transmitting a signal having alternately first and second frequencies comprising: shaping and squaring circuitry which provides in response to the received signal first and second trains of pulses, the two trains having frequencies correspondingly dependent on the frequency of the received signal and the durations of the pulses in each being independent of the durations of the pulses in the other train and small compared with the period of the received signal; a first delay circuit fed with one of said trains of pulses; a second delay circuit fed with one of said trains of pulses; a first coincidence gate circuit having as inputs the output of the first delay circuit and said first train of pulses; and a second coincidence gate circuit having as inputs the output of said second delay circuit and said second train of pulses; the delays of the delay circuits being such that the first coincidence gate circuit produces an output substantially only when the received signal has its first frequency; and the second coincidence gate circuit produces an output substantially only when the received signal has its second frequency.
Claim 3
Dependent Claim
33 words
A receiver as claimed in claim 1 wherein the pulses constituting one of said first and second trains of pulses have a greater duration than those pulses constituting the other train of pulses.
Claim 4
Dependent Claim
101 words
A receiver as claimed in claim 2 wherein at least one of the delay circuits comprises first and second component delay circuits connected via an intermediate coincidence gate circuit, the first component delay circuit being fed with one of said trains of pulses, the intermediate coincidence gate circuit having as inputs the output of said first component delay circuit and one of said trains of pulses, and the second component delay circuit being fed with the output of said intermediate coincidence gate circuit, the output of the second component delay circuit constituting the output of the delay circuit as a whole.
Claim 5
Dependent Claim
64 words
A receiver as claimed in claim 3 wherein the train of pulses supplied to the coincidence gate circuit connected to the output of a delay circuit having first and second component delay circuits is the train of pulses having the shorter duration, and the train of pulses supplied to the associated intermediate coincidence gate circuit is the train of pulses having the longer duration.
Claim 6
Dependent Claim
67 words
A receiver as claimed in claim 4 wherein at least one of said first and second coincidence gate circuits has as an additional input a signal which inhibits the output of that coincidence gate circuit, and which is removed after a predetermined period from the commencement of a period in which the received signal has the frequency at which that gate circuit would otherwise produce an output.
Claim 7
Dependent Claim
30 words
A receiver according to claim 5 wherein said signal which inhibits the output of the coincidence gate circuit is derived from the output of the associated first component delay circuit.
Claim 8
Dependent Claim
70 words
A receiver as claimed in claim 1 wherein at least one delay circuit comprises a monostable circuit arranged to be triggered to its unstable state by the pulses fed to it; and a shaping circuit which produces an output pulse in response to the monostable returning to its stable state so that each pulse triggering said monostable circuit produces a corresponding pulse delayed by the period of the monostable circuit.
Claim 9
Dependent Claim
63 words
A receiver as claimed in claim 7 wherein said first and second trains of pulses are non-coincident, and in respect of each delay circuit, the train of pulses used to trigger the monostable circuit of that delay circuit is different from the train of pulses applied to the coincidence gate circuit whose other input is derived from the output of that delay circuit.
Claim 10
Dependent Claim
52 words
A receiver as claimed in claim 1 wherein said first train of pulses is produced by a first monostable circuit triggered by the received signal, and said second train of pulses is produced by a second monostable circuit triggered by the trailing edges of the pulses of the first train of pulses.
Claim 11
Dependent Claim
22 words
A receiver as claimed in claim 1 wherein said first and second delay circuits are fed with the same train of pulses.
Claim 12
Dependent Claim
67 words
A receiver as claimed in claim 1 wherein the outputs of said first and second coincidence gate circuits provide the inputs of a bistable circuit so that the bistable circuit assumes or remains in one output state in response to an output from the first coincidence gate circuit and assumes or remains in a second output state in response to an output from the second coincidence gate.
References Cited (Backward Citations)
US3233181A
Cited
US3348153A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-22 | 1981-02-21 | 1981-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-22 | 1985-02-21 | 1985-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-22 | 1989-02-21 | 1989-08-23 | $7700.00 | Window Closed / Lapsed |