Electronic timepiece

Claim 1

In an electronic wristwatch having a quartz crystal oscillator circuit adapted to oscillate at a predetermined frequency and produce a high frequency time standard signal, divider circuit means including a multi-stage divider chain for producing low frequency timekeeping signals in response to said high frequency time standard signal and means for the display of time in response to said timekeeping signals, the improvement which comprises said oscillator circuit including means for compensating for changes in temperature to render said high frequency time standard signal produced thereby substantially unaffected by temperature changes; and frequency regulating means coupled to said divider circuit means intermediate said oscillator circuit and divider circuit means for selectively regulating the frequency of said timekeeping signals by effecting continuous adjustment of said high frequency signal without changing the frequency at which said oscillator circuit oscillates, said divider frequency regulating means including inhibit means for inhibiting at least one period of said high frequency signal, said inhibit means including switch means for selecting a coincident count, said inhibit means further including a multi-bit binary counter having one bit for each setting switch means, means for applying said high frequency signal to be inhibited to said binary counter for counting thereby, means for applying a low frequency signal from said divider chain to said binary counter for resetting same, coincident circuit means for receiving the output of said binary counter and the coincidence count from said setting switch means and in response to the coincident states thereof, producing an output pulse; and inhibit circuit means for receiving the output pulse of said coincident circuit means and the low frequency signal and in response thereto inhibiting the transmission to the next divider stage of a number of periods of the high frequency signal corresponding to said coincidence count.