Integrated circuit isolation with mesas and/or insulating substrate

Claim 3

A device as defined in claim 1 wherein said substrate is comprised of single crystal intrinsic semiconductor material.

Claim 4

A device as defined in claim 1 wherein said insulative substrate is of a different material from said overlying material.

Claim 5

A device as defined in claim 3 wherein said substrate is comprised of ceramic material.

Claim 6

A device as defined in claim 4 wherein said substantial impedance results from structural discontinuities extending completely through said overlying material.

Claim 7

A device as defined in claim 3 wherein said substantial impedance results from structural discontinuities extending completely through said overlying material.

Claim 8

A device as defined in claim 3 wherein said substantial impedance results from high resistivity areas within said overlying material between said regions.

Claim 9

A semiconductor circuit complex comprising a wafer of high resistance intrinsic semiconducting material, and a plurality of zones of extrinsic semiconducting material of a first conductivity type disposed in said wafer and separated from each other by said intrinsic material, each of said zones having a semiconducting material of a second conductivity type disposed thereon, forming a P-N junction with said material of a first conductivity type, the device, formed by the semiconducting materials of opposite conductivity type in said zone separated by said P-N junction, having separate means for making contact to it, each of said zones and said devices being electrically isolated from each other by said intrinsic material.

Claim 10

A semiconductor circuit complex comprising a wafer of high resistance intrinsic semiconducting material, and a plurality of zones of extrinsic semiconducting material of a first conductivity type disposed in said wafer and separated from each other by said intrinsic material, each of said zones having a semiconducting material of a second conductivity type disposed thereon, forming a P-N junction with said material of a first conductivity type, the device, formed by the semiconducting materials of opposite conductivity type in said zone separated by said P-N junction, having separate means for making contact to it, each of said zones and said devices being electrically isolated from each other by said intrinsic material.

Claim 11

A semiconductor integrated circuit device comprising a semiconductor substrate, a plurality of mesas of extrinsic semiconductor material located on a major face of said substrate and containing independent circuit components, at least some of the mesas including elongated regions of semiconductor material of a conductivity type opposite that of underlying semiconductor material formed by the introduction of conductivity-type-determining impurities, the elongated regions providing current paths generally parallel to said face, at least some of the means including active circuit components which have regions of semiconductor material of a conductivity type opposite that of underlying semiconductor material formed by the introduction of conductivity-type-determining impurities, parts of said regions of active circuit components being in at least some instances integrally joined with parts of the elongated regions, said substrate including a continuous region of uniform semiconductor material which provides a support for all of said mesas and said independent circuit components and being inactive as a part of any of said circuit components.

Claim 12

A semiconductor integrated circuit device comprising a semiconductor substrate, a plurality of mesas of extrinsic semiconductor material located on a major face of said substrate and containing independent circuit components, at least some of the mesas including elongated regions of semiconductor material of a conductivity type opposite that of underlying semiconductor material formed by the introduction of conductivity-type-determining impurities, the elongated regions providing current paths generally parallel to said face, at least some of the means including active circuit components which have regions of semiconductor material of a conductivity type opposite that of underlying semiconductor material formed by the introduction of conductivity-type-determining impurities, parts of said regions of active circuit components being in at least some instances integrally joined with parts of the elongated regions, said substrate including a continuous region of uniform semiconductor material which provides a support for all of said mesas and said independent circuit components and being inactive as a part of any of said circuit components.

Claim 13

An integrated semiconductor circuit comprising a substrate of intrinsic semiconductor material, a plurality of mutually spaced extrinsic semiconductor regions at one face and spaced from the opposite face of said substrate, a substantial impedance existing through said substrate between said extrinsic regions for electrically isolating one from the other; at least one electrical circuit element at least partially in each extrinsic region, each electrical circuit element having a plurality of zones at the surface of the extrinsic region and means at said surface ohmically electrically connecting selected ones of said zones.

Claim 14

An integrated semiconductor circuit comprising a substrate of intrinsic semiconductor material, a plurality of mutually spaced extrinsic semiconductor regions at one face and spaced from the opposite face of said substrate, a substantial impedance existing through said substrate between said extrinsic regions for electrically isolating one from the other; at least one electrical circuit element at least partially in each extrinsic region, each electrical circuit element having a plurality of zones at the surface of the extrinsic region and means at said surface ohmically electrically connecting selected ones of said zones.

Claim 15

An integrated semiconductor circuit according to claim 10 wherein said extrinsic regions comprise separate semiconductor wafers mounted on said one face of said substrate.

Claim 16

An integrated semiconductor circuit comprising a semiconductor substrate, an extrinsic semiconductor region on one face and spaced from the opposite face of said substrate, said extrinsic region being a semiconductor wafer mounted on said one face of said substrate, a plurality of electrical circuit elements having semiconductor zones, all of said zones being wholly within said region and extending to the surface of said region, a substantial impedance existing between said electrical circuit elements for electrically isolating one from the other through said region and through said substrate, and electrical ohmic connections at the surface of said region between selected ones of said zones, said zones extending to the surface of said region.

Claim 17

An integrated semiconductor circuit comprising a semiconductor substrate, an extrinsic semiconductor region on one face and spaced from the opposite face of said substrate, said extrinsic region being a semiconductor wafer mounted on said one face of said substrate, a plurality of electrical circuit elements having semiconductor zones, all of said zones being wholly within said region and extending to the surface of said region, a substantial impedance existing between said electrical circuit elements for electrically isolating one from the other through said region and through said substrate, and electrical ohmic connections at the surface of said region between selected ones of said zones, said zones extending to the surface of said region.

Claim 18

An integrated circuit comprising a semiconductor substrate of intrinsic semiconductor material, an extrinsic semiconductor region on one face and spaced from the opposite face of said substrate, a plurality of electrical circuit elements having semiconductor zones, all of said zones being wholly within said region and extending to the surface of said region, a substantial impedance existing between said electrical circuit elements for electrically isolating one from the other through said region and through said substrate, and electrical ohmic connections at the surface of said region between selected ones of said zones, said zones extending to the surface of said region.

Claim 19

An integrated circuit comprising a semiconductor substrate of intrinsic semiconductor material, an extrinsic semiconductor region on one face and spaced from the opposite face of said substrate, a plurality of electrical circuit elements having semiconductor zones, all of said zones being wholly within said region and extending to the surface of said region, a substantial impedance existing between said electrical circuit elements for electrically isolating one from the other through said region and through said substrate, and electrical ohmic connections at the surface of said region between selected ones of said zones, said zones extending to the surface of said region.