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US4042944A Expired / Lapsed US ⏱️ 0.0 years remaining

Monostable multivibrator

Assignee: Sony Corp
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Filing: 1975-04-25
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Granted: 1977-08-16
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Expires: 1995-04-25
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Abstract

Abstract A monostable multivibrator having a novel four terminal semiconductor device with a generally V-shaped emitter grounded current amplification characteristic. Means are provided to bias the operation of the device to a low point on the characteristic, to provide a trigger signal to the base of the semiconductor device for placing the device in a conducting state and, through the operation of a capacitor coupled between the gate and collector terminals, to shift the operation of the device to a high level on the emitter-grounded current amplification characteristic thereby sharply decreasing the output voltage obtained at the collector. Discharge circuit means are provided for the capacitor to gradually reduce the gate voltage and to shift the operation of the device back to the low circuit point thereby reducing the collector current and suddenly increasing the collector voltage.

Inventors

  • 👤 Tadao Yoshida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 21:47
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/35; H10; H10D; H10D99/00

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 252 words
A monostable multivibrator circuit comprising: a semiconductor device having a first semiconductor region of one conductivity type, a second semiconductor region of the opposite conductivity type adjacent said first region with a first semiconductor junction therebetween, a third semiconductor region of the same conductivity type of said first region adjacent said second region with a second semiconductor junction therebetween, first, second and third terminals coupled to said first, second and third regions, respectively; a fourth terminal connected to said semiconductor device and having at least a portion thereof located adjacent to said first region at a position which is spaced from the said first terminal, and an insulating layer separating said fourth terminal from said first region, an emitter grounded current amplification of said device being adjustable from a relatively high value to a relatively low value by changing a voltage on said fourth terminal, means for applying a trigger signal to the second terminal of said semiconductor device, a circuit branch containing a capacitor, which branch connects the third and fourth terminals, a predetermined bias being applied to said fourth terminal which is chosen such that in the absence of the trigger signal and in a steady state condition said current amplification is substantially at said relatively low value, means for applying a power source across said first and third terminals of said device, and second means coupled to said second terminal for biasing said device into a conducting state when said current amplification is substantially at said relatively high value.
Claim 2
Dependent Claim 252 words
A monostable multivibrator circuit comprising: a semiconductor device having a first semiconductor region of one conductivity type, a second semiconductor region of the opposite conductivity type adjacent said first region with a first semiconductor junction therebetween, a third semiconductor region of the same conductivity type of said first region adjacent said second region with a second semiconductor junction therebetween, first, second and third terminals coupled to said first, second and third regions, respectively; a fourth terminal connected to said semiconductor device and having at least a portion thereof located adjacent to said first region at a position which is spaced from the said first terminal, and an insulating layer separating said fourth terminal from said first region, an emitter grounded current amplification of said device being adjustable from a relatively high value to a relatively low value by changing a voltage on said fourth terminal, means for applying a trigger signal to the second terminal of said semiconductor device, a circuit branch containing a capacitor, which branch connects the third and fourth terminals, a predetermined bias being applied to said fourth terminal which is chosen such that in the absence of the trigger signal and in a steady state condition said current amplification is substantially at said relatively low value, means for applying a power source across said first and third terminals of said device, and second means coupled to said second terminal for biasing said device into a conducting state when said current amplification is substantially at said relatively high value.
Claim 3
Dependent Claim 30 words
A circuit in accordance with claim 1 wherein said device is operated as an emitter grounded four terminal device and an impedance is disposed in series with said predetermined bias.
Claim 4
Dependent Claim 95 words
A circuit in accordance with claim 1 wherein said second means causes said device to develop a steady state voltage across said first and third terminals, said trigger signal being a pulse having a substantially higher value than said second means and causing said device to operate at a relatively high level resulting in a sharply reduced voltage across said first and third terminals, whereby said fourth terminal voltage is shifted by the operation of said capacitor to a value which places the emitter grounded amplification characteristic of said device at a relatively high level.
Claim 5
Dependent Claim 25 words
A circuit in accordance with claim 3 wherein the discharge time of said capacitor is less than the period of repetition of the trigger signal.
Claim 6
Dependent Claim 90 words
A circuit in accordance with claim 1, wherein said first and third regions of the semiconductor device each have at least a first portion concentrations of substantially the same order of magnitude, said first region being provided with a second portion having an impurity concentration higher than said first portion of the first region at a position spaced from said first junction by a distance which is smaller than the diffusion distance of the minority carriers, and said fourth terminal comprising a gate electrode which overlies only said first region.

References Cited (Backward Citations)

GB906036A Cited
US3204160A Cited
US3289009A Cited
US3407313A Cited
US3382375A Cited
US3397326A Cited
US3513333A Cited
US3727082A Cited
US3836797A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-08-15 1981-02-14 1981-08-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-08-15 1985-02-14 1985-08-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-08-15 1989-02-14 1989-08-16 $7700.00 Window Closed / Lapsed

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