Automatic gain control circuit

Claim 2

An automatic gain control circuit comprising: a first pair of transistors whose emitters are commonly coupled to one end of common impedance means, the other end of said common impedance means being connected to a reference potential source; a second pair of transistors whose emitters are commonly coupled to a collector of one of said first pair of transistors, the collector of the other of said first pair of transistors being connected to a source of operating potential; load impedance means for coupling the collector of one of said second pair of transistors to said source of operating potential, the collector of the other of said second pair of transistors being directly connected to said source of operating potential; means for applying an input signal to said one of said first pair of transistors; and means for supplying a gain control signal to the base of either transistor in each pair of said first pair of transistors and said second pair of transistors so as to increase the collector bias current of said one of said first pair of transistors and conversely decrease the collector bias current of said one of said second pair of transistors in response to an increase of said input signal.

Claim 3

The circuit according to claim 1, wherein said means for supplying said gain control signal is coupled to the base of said other of said first pair of transistors and to the base of said one of said second pair of transistors.

Claim 4

The circuit according to claim 2, wherein said means for supplying said gain control signal includes the collector-emitter path of a fifth transistor which is connected between said base of said other of said first pair of transistors and said reference potential source, and a resistance which is connected between said base of said other of said first pair of transistors and a first bias potential source, the base of said fifth transistor receiving said gain control signal.

Claim 5

The circuit according to claim 3, further including a level transformation circuit means for coupling the base of said fifth transistor and the base of said one of said second pair of transistors to said gain control signal.

Claim 6

The circuit according to claim 4, wherein said level transformation circuit is composed of an emitter follower type transistor amplifier and a grounded emitter type transistor amplifier, and said gain control signal is applied commonly to the bases of the two transistor amplifiers.

Claim 7

A gain-controlled amplifier circuit comprising: a first differential pair of transistors whose emitters are commonly coupled in a differential amplifier configuration; a second differential pair of transistors whose emitters are commonly coupled to a collector of one of said first differential pair of transistors; means for supplying an input signal to the base of said one of said first differential pair of transistors; means for deriving an output signal from a collector of one of said second differential pair of transistors; means for applying a gain control signal to a base of either transistor in said first differential pair of transistors so as to change the collector bias currents of said first differential pair of transistors in response to an input signal level when the level of said input signal does not exceed a predetermined first value, whereby automatic gain control is achieved by said first differential pair of transistors at the input signal levels not exceeding said predetermined first value; and means for applying said gain control signal to the base of either transistor in said second differential pair of transistors so as to change the collector bias currents of said second differential pair of transistors in response to an input signal level when the level of said input signal exceeds said predetermined first value, whereby automatic gain control is achieved by said second differential pair of transistors at the input signal levels exceeding said predetermined first value.

Claim 8

A gain-controlled amplifier circuit comprising: a first differential pair of transistors whose emitters are commonly coupled in a differential amplifier configuration; a second differential pair of transistors whose emitters are commonly coupled to a collector of one of said first differential pair of transistors; means for supplying an input signal to the base of said one of said first differential pair of transistors; means for deriving an output signal from a collector of one of said second differential pair of transistors; means for applying a gain control signal to a base of either transistor in said first differential pair of transistors so as to change the collector bias currents of said first differential pair of transistors in response to an input signal level when the level of said input signal does not exceed a predetermined first value, whereby automatic gain control is achieved by said first differential pair of transistors at the input signal levels not exceeding said predetermined first value; and means for applying said gain control signal to the base of either transistor in said second differential pair of transistors so as to change the collector bias currents of said second differential pair of transistors in response to an input signal level when the level of said input signal exceeds said predetermined first value, whereby automatic gain control is achieved by said second differential pair of transistors at the input signal levels exceeding said predetermined first value.

Claim 9

A gain-controlled amplifier circuit according to claim 6, wherein said gain control signal is applied to the base of the other transistor of said first differential pair of transistors and to the base of said one transistor of said second differential pair of transistors with opposite phases.

Claim 10

A gain-controlled amplifier circuit according to claim 7, wherein said gain control signal is provided by a level transformation circuit means comprising an emitter follower type transistor amplifier and a grounded-emitter type transistor amplifier, a general gain control signal being applied commonly to the bases of the two transistor amplifiers.

Claim 11

A gain-controlled amplifier circuit according to claim 7, further including a fifth transistor connected between the base of said other transistor of said first differential pair of transistors and reference potential source, and a resistance connected between the base to which said fifth transistor is connected and a bias potential source, the base of said fifth transistor receiving said gain control signal.