US3838210A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic gain control system and amplifier of controllable gain
Assignee: RCA Licensing Corp
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Filing: 1973-10-01
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Granted: 1974-09-24
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Expires: 1993-10-01
Abstract
Abstract An automatic gain control system incorporating a novel amplifier of controllable gain is described. The amplifier is d.c. coupled throughout and capable of wideband operation. It employs a cascoded differential transistor amplifier for producing the principal voltage gain supplemented by input and output emitter followers. Gain control is achieved by the application of gain control potentials to the bases of the upper rank transistors. Gain reduction is produced first in the upper rank by the controlled degeneration produced by a pair of nonlinear impedances in series with the emitter leads of the upper rank transistors, and sequentially in the lower rank transistors by the controlled degeneration produced by two pairs of nonlinear impedances coupled in a degenerative feedback path about the lower rank transistors and in the input circuit to a pair of input emitter followers. In addition, the amplifier produces an indication of gain control action which, when the amplifier is used as an intermediate frequency amplifier of a television system, permits one to derive a second gain control signal, which after thresholding may be used for further gain reduction in the tuner. The amplifier is adapted for integrated circuit fabrication.
Inventors
- 👤 W Peil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:09
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/52; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3052; H03G3/3068
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
346 words
An amplifier of controllable gain comprising: a. a first pair of transistors each having base, emitter and collector electrodes connected in emitter follower configuration, and having an input circuit for differentially applying the input signal to the bases thereof with the output signal appearing differentially at the emitters thereof, b. a second pair of transistors each having base, emitter and collector electrodes connected in differential amplifier configuration, each having a base d.c. coupled to an emitter of one of said first pair of transistors; and each having a load circuit including a first forward poled diode and resistance in shunt therewith coupled to each collector, c. a third pair of transistors each having base, emitter and collector electrodes connected in cascode with said second transistor pair, each emitter of said third pair being d.c. coupled through one of said load circuits to a collector of said second pair in a current path branched at said collector; the output signal appearing differentially at the collectors of said third pair, d. a feedback circuit for the associated transistors of said first and second pairs including a second diode pair, each diode being connected between the collector of a transistor of said second pair and the base of the associated one of said first pair of transistors and forming a first one of said collector connected branches, the diodes of said second pair being normally reversely poled, said input circuit providing a low impedance path for forward current through said second diode pair, e. means for coupling a gain control voltage to the bases of said third transistor pair for reducing the emitter current of said third transistor pair and by emitter follower action, reducing the collector voltage of said second transistor pair, and f. control means for sequentially reducing the forward Bias of said first diode pair to cause gain reducing degeneration in said third transistor pair, and next for forward biasing said second, normally reversely poled second diode pair to cause gain reducing degeneration in said first and second transistor pairs as said gain control voltage increases.
Claim 2
Dependent Claim
346 words
An amplifier of controllable gain comprising: a. a first pair of transistors each having base, emitter and collector electrodes connected in emitter follower configuration, and having an input circuit for differentially applying the input signal to the bases thereof with the output signal appearing differentially at the emitters thereof, b. a second pair of transistors each having base, emitter and collector electrodes connected in differential amplifier configuration, each having a base d.c. coupled to an emitter of one of said first pair of transistors; and each having a load circuit including a first forward poled diode and resistance in shunt therewith coupled to each collector, c. a third pair of transistors each having base, emitter and collector electrodes connected in cascode with said second transistor pair, each emitter of said third pair being d.c. coupled through one of said load circuits to a collector of said second pair in a current path branched at said collector; the output signal appearing differentially at the collectors of said third pair, d. a feedback circuit for the associated transistors of said first and second pairs including a second diode pair, each diode being connected between the collector of a transistor of said second pair and the base of the associated one of said first pair of transistors and forming a first one of said collector connected branches, the diodes of said second pair being normally reversely poled, said input circuit providing a low impedance path for forward current through said second diode pair, e. means for coupling a gain control voltage to the bases of said third transistor pair for reducing the emitter current of said third transistor pair and by emitter follower action, reducing the collector voltage of said second transistor pair, and f. control means for sequentially reducing the forward Bias of said first diode pair to cause gain reducing degeneration in said third transistor pair, and next for forward biasing said second, normally reversely poled second diode pair to cause gain reducing degeneration in said first and second transistor pairs as said gain control voltage increases.
Claim 3
Dependent Claim
134 words
An amplifier of controllable gain as set forth in claim 1, wherein said control means includes means for stabilizing the emitter current in said second transistor pair as gain is reduced, sand means comprising: a. a current sensing resistance coupled in the emitter path of said second transistor pair, b. a current sensing transistor amplifier having its base coupled to said resistance, and producing an amplified indication of the emitter current in said second transistor pair, and c. stabilizing means responsive to said amplified current indication for stabilizing the voltage at the bases of said first transistor pair and for injecting current into a collector connected branch of each transistor of said second pair to stabilize the emitter current in said second transistor pair against reductions in emitter current of said third transistor pair.
Claim 4
Dependent Claim
48 words
The combination set forth in claim 2 wherein said stabilizing means comprises a first current injecting transistor in emitter follower configuration, whose base is coupled to the output of said current sensing transistor amplifier, and whose emitter id d.c. coupled to the collectors of said second transistor pair.
Claim 5
Dependent Claim
212 words
The combination set forth in claim 3 wherein: a. said input circuit is a double ended input circuit comprising a resistance serially connected in each signal path and a second pair of serially connected resistors and a third pair of serially connected diodes, with one like electrode of one diode connected to a like electrode of the other diode, said last recited resistpr pair and said third diode pair shunting the bases of said first transistor pair and being joined at their interconnection points to form an a.c. ground of variable d.c. potential for said first transistor pair, and wherein b. said stabilizing means further includes a second current injecting transistor, in base input configuration, whose emitter is coupled to said a.c. ground; the input junction of said current injecting transistor, said second diode pair and said third diode pair being similarly poled for substantial serial current flow, whereby upon application of a predetermined gain control voltage which reduces the collector potential of said second pair of transistors that forward bias to said second diode pair is provided, such that said second diode pair, said third diode pair, and said current injecting transistor become simultaneously conductive to provide additional current into a collector connected branch of each transistor of said second pair.
Claim 6
Dependent Claim
73 words
The combination set forth in claim 4 wherein said first current injecting transistor is adjusted to inject current into said branch prior to current injection from said second current injecting transistor, whereby the forward bias of said first diode pair is removed prior to forward biasing of said second diode pair to cause gain reduction in said upper rank transistors to be completed before gain reduction in said lower rank transistors is initiated.
Claim 7
Dependent Claim
70 words
The combination set forth in claim 4 wherein said last recited resistor pair has like resistance values, proportioned to provide a small input signal loading to permit high gain operation of said lower rank transistor pair when said second diode pair are nonconductive, said third diode pair upon becoming conductive simultaneously with said second diode pair, causing an increase in said input signal loading and producing a consequent gain reduction.
Claim 8
Dependent Claim
48 words
The combination set forth in claim 6 wherein a. said amplifier of controllable gain is an intermediate frequency amplifier of a television receiver, said combination having in addition thereto b. a tuner, also of controllable gain, connected to be responsiVe to current from said second current injecting transistor.
Claim 9
Dependent Claim
102 words
The combination set forth in claim 7 having in addition thereto a. a first thresholding means responsive to an AGC voltage developed from sensing detected synchronizing pulses in a received television signal for application of a gain control potential to said intermediate frequency amplifier, and wherein b. a second thresholding means is provided for application of a gain control potential to said tuner, said second thresholding means applying a control potential when the current in said second current injecting transistor exceeds a predetermined threshold level corresponding to a predetermined amount of gain withdrawal from the lower rank of said intermediate frequency amplifier.
Claim 10
Dependent Claim
24 words
The combination set forth in claim 8 wherein said second thresholding means derives its current from the collector of said second current injecting transistor.
References Cited (Backward Citations)
US3641450A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |