Solid state relay circuit

Claim 2

A solid state relay circuit of the alternating impulse type comprising a thyristor having a pair of primary terminals and a gate terminal; means for connecting a load and an AC source voltage in series with said primary terminals; and a triggering circuit connected to said gate terminal for triggering the thyristor into conduction to provide a current to said load, said triggering circuit comprising means for receiving an input trigger signal, a pulse shaping circuit connected to said last named means for shaping said input trigger signal into a squared pulse, a toggle flip-flop having two output states connected to the output of said pulse shaping circuit, said flip-flop being connected to said pulse shaping circuit so as to provide alternate output states for successive input pulses, and an optically isolated switch connected between the output of said flip-flop and said gate terminal of said thyristor, said switch having a power supply separate from the power supplies for the other components in said triggering circuit.

Claim 3

A solid state relay circuit as set forth in claim 1 wherein said switch comprises a transistor.

Claim 4

A solid state relay circuit as set forth in claim 2 wherein said switch comprises a pair of transistors connected in the Darlington configuration with the base input thereto being optically connected with the output of said flip-flop.

Claim 5

A solid state relay circuit as set forth in claim 1 wherein said input trigger signal is an AC signal and said means for receiving said input trigger signal comprises an AC to DC converter.

Claim 6

A solid state relay circuit as set forth in claim 1 wherein said pulse shaping circuit includes an optically isolated switch, a time delay circuit, and a pulse squaring circuit.

Claim 7

A solid state relay circuit as set forth in claim 5 wherein said optically isolated switch comprises a transistor with the base input thereto being optically connected with the output of said means for receiving said input trigger signal.

Claim 8

A solid state relay circuit of the alternating impulse type comprising a pair of thyristors each having a first and a second primary terminal and a gate terminal; a pair of loads each being connected in series with said first primary terminal of one of said thyristors; means for connecting an AC source voltage in series with said second primary terminals of said thyristors; and a triggering circuit connected to said gate terminals for alternately triggering said thyristors into conduction to alternately provide currents to said loads, said triggering circuit comprising means for receiving an input trigger signal, a pulse shaping circuit connected to said last named means for shaping said input trigger signal into a squared pulse, a toggle flip-flop having two output states connected to the output of said pulse shaping circuit, said flip-flop being connected to said pulse shaping circuit so as to provide alternate output states for successive input pulses, an optically isolated switch connected between the output of said flip-flop and the gate terminals of said thyristors, a power supply for said optically isolated switch separate from the power supplies for the other components in said triggering circuit, and a secondary switching element connected between said optically isolated switch and one of said gate terminals to provide a gate activating current at said one gate terminal when said optically isolated switch is not conducting a gate activating current to the other of said gate terminals and to block the gate activating current to said one gate terminal when said optically isolated switch is conducting a gate activating current to said other gate terminal.

Claim 9

A solid state relay circuit of the alternating impulse type comprising a pair of thyristors each having a first and a second primary terminal and a gate terminal; a pair of loads each being connected in series with said first primary terminal of one of said thyristors; means for connecting an AC source voltage in series with said second primary terminals of said thyristors; and a triggering circuit connected to said gate terminals for alternately triggering said thyristors into conduction to alternately provide currents to said loads, said triggering circuit comprising means for receiving an input trigger signal, a pulse shaping circuit connected to said last named means for shaping said input trigger signal into a squared pulse, a toggle flip-flop having two output states connected to the output of said pulse shaping circuit, said flip-flop being connected to said pulse shaping circuit so as to provide alternate output states for successive input pulses, an optically isolated switch connected between the output of said flip-flop and the gate terminals of said thyristors, a power supply for said optically isolated switch separate from the power supplies for the other components in said triggering circuit, and a secondary switching element connected between said optically isolated switch and one of said gate terminals to provide a gate activating current at said one gate terminal when said optically isolated switch is not conducting a gate activating current to the other of said gate terminals and to block the gate activating current to said one gate terminal when said optically isolated switch is conducting a gate activating current to said other gate terminal.

Claim 10

A solid state relay circuit as set forth in claim 7 wherein said optically isolated switch comprises a first transistor with the base input thereto being optically connected with the output of said flip-flop and wherein said secondary switching element comprises a second transistor with the base input thereof being connected between said power supply and the collector input of said first transistor, and means in said base input of the second transistor for biasing said second transistor off when said first transistor is conducting.

Claim 11

A solid state relay circuit as set forth in claim 8 wherein said thyristors comprise triacs.

Claim 12

A solid state relay circuit as set forth in claim 7 wherein said input trigger signal is an AC signal and said means for receiving said input trigger signal comprises an AC to DC converter.

Claim 13

A solid state relay circuit as set forth in claim 10 wherein said pulse shaping circuit comprises a second optically isolated switch connected to receive the output of said AC to DC converter.

Claim 14

A solid state relay circuit as set forth in claim 11 wherein said pulse shaping circuit further includes a time delay circuit and a pulse squaring circuit serially connected between said second optically isolated switch and said flip flop.

Claim 15

A solid state relay circuit as set forth in claim 11 wherein said second optically isolated switch comprises a pair of transistors connected in the Darlington configuration with the base input thereto being optically connected with the output of said AC to DC converter.