US4041290A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprogram controlled binary decimal coded byte operator device
Assignee: Compagnie Internationale pour l'Informatique CII-Honeywell Bull SA
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Filing: 1975-01-06
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Granted: 1977-08-09
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Expires: 1995-01-06
Abstract
Abstract A microprogram controlled operator device is described which processes bytes each of which is comprised of an equal number of binary-coded decimal figures. The device comprises first and second byte stores each of a multi-byte capacity, a logical and arithmetical operator circuit having inputs connected to read-out outputs of said stores and having an output to a buffer register and code handling organization, preferably further enabling "raw" byte inputting. An output of the code handling organization is connected to an input of a byte code processing arrangement which includes a multiplexer circuit having outputs to write-in inputs of the first and second stores and having further inputs connected to external data supplying means and to read-out outputs from the said stores. The organization further has an output to the external equipment wherein said device is connected.
Inventors
- 👤 Jean-Louis Fressineau
- 👤 Maurice Hubert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:42
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/492; G06F7/493; G06F7/494; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30025; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3828; G06F2207/492; G06F2207/4924
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
175 words
A microprogram controlled byte operator device for processing strings of bytes wherein each byte has the same number of binary bit quartets comprising in combination: a byte arithmetical and logical operator circuit having first and second byte inputs and a byte output; a multi-byte register means connected to the output of said operator circuit; first and second addressable byte stores, each capable of storing a plurality of bytes and having a byte write-in input and a byte readout output, the byte readout outputs of said first and second stores being respectively connected to said first and second byte inputs of said arithmetical and logical operator circuit; input means adapted to sequentially receive the bytes of the strings of bytes; a plural input multiplexer circuit having a plurality of byte inputs and a plurality of quartet inputs and having an output connected to the byte write-in inputs of said first and second addressable byte stores, one of said byte inputs being connected to a byte output of said multi-byte register means and of said input means.
Claim 2
Dependent Claim
175 words
A microprogram controlled byte operator device for processing strings of bytes wherein each byte has the same number of binary bit quartets comprising in combination: a byte arithmetical and logical operator circuit having first and second byte inputs and a byte output; a multi-byte register means connected to the output of said operator circuit; first and second addressable byte stores, each capable of storing a plurality of bytes and having a byte write-in input and a byte readout output, the byte readout outputs of said first and second stores being respectively connected to said first and second byte inputs of said arithmetical and logical operator circuit; input means adapted to sequentially receive the bytes of the strings of bytes; a plural input multiplexer circuit having a plurality of byte inputs and a plurality of quartet inputs and having an output connected to the byte write-in inputs of said first and second addressable byte stores, one of said byte inputs being connected to a byte output of said multi-byte register means and of said input means.
Claim 3
Dependent Claim
15 words
A byte operator device according to claim 1 wherein said input means comprises register means.
Claim 4
Dependent Claim
49 words
A byte operator device according to claim 1 wherein a first gate is connected between the output of said multi-byte register means and a byte input of the plural input multiplexer circuit and a second gate connects said multi-byte register means and an output lead from said operator device.
Claim 5
Dependent Claim
33 words
A byte operator device according to claim 1, wherein said first and second addressable byte stores each has a quartet read-out output connected to a quartet input of said plural input multiplexer circuit.
Claim 6
Dependent Claim
43 words
A byte operator device according to claim 1 including a byte decimalization circuit having a byte input connected to the output of said input means and bit outputs connected to a plurality of byte and quartet inputs of said plural input multiplexer circuit.
Claim 7
Dependent Claim
48 words
A byte operator device according to claim 5, wherein said byte decimalization circuit comprises first and second modulo-2 adder circuits, each adding a digital code "6" to each quartet of a byte and wherein said byte arithmetical and logical operator circuit includes a digital code "6" subtracting circuit.
Claim 8
Dependent Claim
61 words
A byte operator device according to claim 1, wherein two-input multiplexer circuits, each having an input to a quartet readout output of said addressable byte stores and each having its other input connected to a parameter code source and each having a control input, have their outputs respectively connected to the said quartet inputs of the said plural input multiplexer circuit.
Claim 9
Dependent Claim
29 words
A byte operator device according to claim 7 wherein one of said parameter code sources comprises a register storing a code representing a rank of field of a microprogram.
Claim 10
Dependent Claim
111 words
A byte operator device according to claim 7, comprising, in combination: a first code register loaded with a microprogram code defining a number of elementary steps to be executed by the byte operator circuit; a second code register loaded with a microinstruction code defining the rank of the step defined by each microinstruction in the microprogram; means decrementing by one unit on the execution of each elementary step of the microprogram, the code of the first code register; a code comparator, having first and second inputs connected to outputs of said first and second code registers and having an output connected to the control inputs of the said two-input multiplexor circuits.
Claim 11
Dependent Claim
22 words
A byte operator according to claim 9 wherein input gates connect the said first and second code registers to input register means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-08 | 1981-02-07 | 1981-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-08 | 1985-02-07 | 1985-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-08 | 1989-02-07 | 1989-08-09 | $7700.00 | Window Closed / Lapsed |