Digital video signal processing circuit

Claim 1

A digital radar video averaging circuit for processing input periodic two-bit digital signals, each period comprising n two-bit signals, said circuit comprising: a. Four dual n-bit shift registers, each dual shift register having a most significant bit input terminal, a least significant bit input terminal, a most significant bit output terminal, a least significant bit output terminal, and a clock input terminal, the said two-bit digital signals being applied simultaneously to the four dual shift registers through parallel connections of the least significant bit and most significant bit input terminals; b. Clock means to enable the four dual shift registers to sequentially store successive periods of the input signals such that a first period of n two-bit signals is stored in a first shift register, the second period of n two-bit signals is stored in a second shift register, the third period of n two-bit signals is stored in a third shift register and the fourth period of n two-bit signals is stored in a fourth shift register; c. Clock means to shift the four dual shift registers simultaneously after the fourth shift register has been filled; d. First addition and division means to sum and divide by two the outputs of said first and second dual shift registers; e. Second addition and division means to sum and divide by two the outputs of said third and fourth dual shift registers; f. Third addition and division means to sum and divide by two the output of the first and second addition and division means, to produce an averaged two-bit digital output signal.