US3794994A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Feedback integrator with pedestal elimination
Assignee: United States Department of the Navy
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Filing: 1972-06-29
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Granted: 1974-02-26
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Expires: 1992-06-29
Abstract
Abstract A digital feedback integrator, especially adapted to provide increased target detection ability in radar systems. The feedback integrator is employed in the signal processing circuitry and compensates for arithmetic truncation errors by advantageously avoiding a final truncation pedestal in the integrating output.
Inventors
- 👤 L Leibowitz
- 👤 R Baldauf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:39
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/18; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/292; G01S7/2923; G01S7/2926
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
107 words
In a system for integrating radar video wherein a digital word, corresponding to said video, is applied to a shift register by way of an adder, the output of said shift register being coupled back to said adder by way of multiplier means, the improvement comprising: circuit means coupled to said multiplier means for eliminating a truncation pedestal in the integrating system output; said circuit means including an n + d bit binary adder means, where n is any positive integer and d is the digital word size such that the integrated output level is able to decay below a level representing the quantity 2n - 1.
Claim 2
Dependent Claim
107 words
In a system for integrating radar video wherein a digital word, corresponding to said video, is applied to a shift register by way of an adder, the output of said shift register being coupled back to said adder by way of multiplier means, the improvement comprising: circuit means coupled to said multiplier means for eliminating a truncation pedestal in the integrating system output; said circuit means including an n + d bit binary adder means, where n is any positive integer and d is the digital word size such that the integrated output level is able to decay below a level representing the quantity 2n - 1.
Claim 3
Dependent Claim
48 words
The device as claimed in claim 1 wherein said binary adder means includes carry means such that a carry into the n + d bit binary adder means is a logical ''''0'''' unless the output of said shift register is representative of a decimal magnitude of 0 or
Claim 4
Dependent Claim
21 words
The device as claimed in claim 2 wherein said carry means comprises an inverter means in combination with an AND gate.
References Cited (Backward Citations)
US3246324A
Cited
US3422435A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-25 | 1977-08-27 | 1978-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-25 | 1981-08-27 | 1982-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-25 | 1985-08-27 | 1986-02-26 | $7700.00 | Window Closed / Lapsed |