Patent US4040032A successfully refreshed from Google Patents.
US4040032A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peripheral device controller for a data processing system
Assignee: EMC Corp
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Filing: 1976-02-27
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Granted: 1977-08-02
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Expires: 1996-02-27
Abstract
Abstract There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.
Inventors
- 👤 Philip Michael Kreiker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:57
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; G06F1/00; G06F1/04; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
455 words
In a data processing system including (a) a CPU, (b) a main memory interfacing with said CPU, (c) I/O means, including an I/O bus having a plurality of peripheral device transceivers displaced along said bus and each of said transceivers being directly connected to said bus, for directly connecting between said CPU and a like plurality of peripheral devices, and (d) a clock source for providing timing pulses to said system, device controller means contained within said I/O means for transmitting and receiving signals between (i) each of said plurality of peripheral devices and (ii) both each respective one of said plurality of transceivers and said CPU, said device controller means comprising a like plurality of individual device controllers, each respective one of said controllers comprising: shift register means for serially receiving an input group of said signals from said respective one of said transceivers and for serially transmitting an output group of said signals to said respective one of said transceivers; first bus means for parallel conducting representations of certain of said input group of signals from said shift register means to at least the respective peripheral device; second bus means for parallel conducting representations of certain of said output group of signals from at least said respective peripheral device to at least said shift register means; other register means connected between said first bus means and said second bus means for (1) parallel receiving representations of said input group of signals from said first bus means, (2) temporarily storing said representations, and (3) parallel transmitting representations of said output group of signals to said second bus means; instruction register means connected from said first bus means for storing an instruction derived from said representations of certain of said input group of signals; programmable logic array means, having stored therein information representative of logic states of said respective one of said controllers, for controlling said respective one of said device controllers to operate in one of said logic states; state change logic means, responsive to at least (1) said one of said logic states from said programmable logic array means and (2) said instruction from said instruction register means, for selecting another of said logic states as the next successive one of said logic states after termination of said one of said states; and bypass means connected from said second bus means and from a respective one of said devices for conducting other of said signals relating to requests by said one of said plurality of peripheral devices and by said CPU for certain operations of said main memory directly between said respective one of said controllers and said CPU in a conductive path that does not include said respective one of said transceivers.
Claim 2
Dependent Claim
455 words
In a data processing system including (a) a CPU, (b) a main memory interfacing with said CPU, (c) I/O means, including an I/O bus having a plurality of peripheral device transceivers displaced along said bus and each of said transceivers being directly connected to said bus, for directly connecting between said CPU and a like plurality of peripheral devices, and (d) a clock source for providing timing pulses to said system, device controller means contained within said I/O means for transmitting and receiving signals between (i) each of said plurality of peripheral devices and (ii) both each respective one of said plurality of transceivers and said CPU, said device controller means comprising a like plurality of individual device controllers, each respective one of said controllers comprising: shift register means for serially receiving an input group of said signals from said respective one of said transceivers and for serially transmitting an output group of said signals to said respective one of said transceivers; first bus means for parallel conducting representations of certain of said input group of signals from said shift register means to at least the respective peripheral device; second bus means for parallel conducting representations of certain of said output group of signals from at least said respective peripheral device to at least said shift register means; other register means connected between said first bus means and said second bus means for (1) parallel receiving representations of said input group of signals from said first bus means, (2) temporarily storing said representations, and (3) parallel transmitting representations of said output group of signals to said second bus means; instruction register means connected from said first bus means for storing an instruction derived from said representations of certain of said input group of signals; programmable logic array means, having stored therein information representative of logic states of said respective one of said controllers, for controlling said respective one of said device controllers to operate in one of said logic states; state change logic means, responsive to at least (1) said one of said logic states from said programmable logic array means and (2) said instruction from said instruction register means, for selecting another of said logic states as the next successive one of said logic states after termination of said one of said states; and bypass means connected from said second bus means and from a respective one of said devices for conducting other of said signals relating to requests by said one of said plurality of peripheral devices and by said CPU for certain operations of said main memory directly between said respective one of said controllers and said CPU in a conductive path that does not include said respective one of said transceivers.
Claim 3
Dependent Claim
348 words
In a data processing system including a CPU for processing said data, a master clock for providing timing pulses to said system, a main memory interfacing with said CPU, at least one peripheral device for providing inputs to and receiving outputs from said system, and I/O means for conducting unmodulated signals directly between said CPU and said at least one peripheral device, said I/O means comprising an I/O bus and at least one peripheral device transceiver with its respective device controller, said transceiver being connected from said I/O bus and said controller being connected between said transceiver and said device, said controller comprising: shift register means for serially receiving an input group of said signals from said transceiver and for serially transmitting an output group of said signals to said transceiver; first bus means for parallel conducting representations of said input group of signals from said shift register means to said at least one peripheral device; second bus means for parallel conducting representations of said output group of signals from said at least said peripheral device to at least said shift register means; other register means connected between said first bus means and said second bus means for (1) parallel receiving representations of said input group of signals from said first bus means, (2) temporarily storing said representations, and (3) parallel transmitting representations of said output group of signals to said second bus means; instruction register means connected from said first bus means for storing an instruction derived from said representations of said input group of signals; logic means, having stored therein information representative of logic states of said controller and responsive to operation of said register means, for controlling said register means to operate in one of said logic states and for selecting the next successive one of said logic states, and, said logic means including a programmable logic array, and state change logic means for addressing said programmable logic array responsive to said instruction stored in said instruction register means and to a representation of said one of said logic states from said programmable logic array.
Claim 4
Dependent Claim
348 words
In a data processing system including a CPU for processing said data, a master clock for providing timing pulses to said system, a main memory interfacing with said CPU, at least one peripheral device for providing inputs to and receiving outputs from said system, and I/O means for conducting unmodulated signals directly between said CPU and said at least one peripheral device, said I/O means comprising an I/O bus and at least one peripheral device transceiver with its respective device controller, said transceiver being connected from said I/O bus and said controller being connected between said transceiver and said device, said controller comprising: shift register means for serially receiving an input group of said signals from said transceiver and for serially transmitting an output group of said signals to said transceiver; first bus means for parallel conducting representations of said input group of signals from said shift register means to said at least one peripheral device; second bus means for parallel conducting representations of said output group of signals from said at least said peripheral device to at least said shift register means; other register means connected between said first bus means and said second bus means for (1) parallel receiving representations of said input group of signals from said first bus means, (2) temporarily storing said representations, and (3) parallel transmitting representations of said output group of signals to said second bus means; instruction register means connected from said first bus means for storing an instruction derived from said representations of said input group of signals; logic means, having stored therein information representative of logic states of said controller and responsive to operation of said register means, for controlling said register means to operate in one of said logic states and for selecting the next successive one of said logic states, and, said logic means including a programmable logic array, and state change logic means for addressing said programmable logic array responsive to said instruction stored in said instruction register means and to a representation of said one of said logic states from said programmable logic array.
Claim 5
Dependent Claim
24 words
The system of claim 2 and wherein said state change logic means includes means for receiving and for being timed by said timing signals.
Claim 6
Dependent Claim
44 words
The system of claim 3 further including bypass means connected from said second bus means for conducting said unmodulated signals directly between said CPU and said controller for certain operations of said main memory in a conductive path that does not include said transceiver.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-01 | 1981-01-31 | 1981-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-01 | 1985-01-31 | 1985-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-01 | 1989-01-31 | 1989-08-02 | $7700.00 | Window Closed / Lapsed |