Logic state analyzer

Abstract

Abstract Clock signals, data words and qualifier signals are received via monitor probes during a data acquisition mode, selected data words being stored in a memory in response to the clock and qualifier signals. The stored data words may then be displayed in a tabular or a map format on a cathode ray tube screen. Data words may be acquired randomly, i.e., in a free-running sampling mode, or acquired selectively by using pattern recognition and delay trigger circuits. Using the tabular display format, data words are displayed as ones and zeroes. Using the map display format, each data word thus acquired is displayed on the CRT screen as a dot during a subsequent display mode. The position of each dot on the CRT screen uniquely identifies its address or state value. The most significant bits determine the vertical position on the CRT screen and the least significant bits determine the horizontal position of the dot. The intensity of the dot indicates the relative frequency of occurrence of that logic state. A trace between dots is utilized as a vector to indicate the sequence in which the data words are acquired, the brightened or intensified end of the vector indicating the direction. The vectors are non-linear so that when logic flow occurs in opposite directions between logic states, the vectors will not overlap and obscure useful information. A cursor is provided to select a map area to be displayed in an expanded map mode, wherein a portion of the map may be displayed on a larger scale. Also, a comparator mode is provided to allow comparison of acquired input data with that stored in an auxiliary memory. ______________________________________ Column TABLE OF CONTENTS No. ______________________________________ Basic Block Diagram Operating Controls and Indicators Desription of the Detailed Block Diagram Table I (Cross-Reference of Block Diagram Elements to Detailed Schematics) Description of Data Input, Temporary Storage and Pattern Recognition Block Diagram Description of the Digital Delay and Trigger Generator Block Diagram Trigger Generator and Delay Generator Circuitry Timing Generator Circuitry The A Memory and Data Index and Control Circuitry -Display Mode Operation Word Intensifying Circuitry Data Routing and Multiplexing Circuitry Display Blanking Circuitry Table II (Multiplexer Control Signals) Data Acquisition Circuitry Display Generator Circuitry Display Output Circuitry Table III (Multiplexer Truth Table) Table IV (Truth Table for Horizontal and Vertical Decoders) Table V (Truth Table for the Horizontal ROM) Appendix A (Description of Signal Mneumonics) ______________________________________ +cl BACKGROUND OF THE INVENTION Engineers developing digital systems find themselves increasingly more interested in digital word flow than in the waveforms of particular signals. For example, instruction and address sequences in a microprocessor are usually of more interest to the designer and diagnostician than the waveform on a signle address or instruction line. Some past efforts have been directed towards providing digital instruments which are capable of producing trigger pulses in response to the detection of selected digital words. This trigger pulse can be used to trigger an oscilloscope or other display device. See, for example, U.S. Pat. No. 3,805,255 by C. Mark Baker entitled "Scanning Light Emitting Diode Display of Digital Information". Other recent efforts have provided a listing of sequential binary words. See, for example, the Hewlett-Packard Journal of January 1974. SUMMARY OF THE INVENTION In accordance with the preferred embodiment of the present invention, digital words are selectively acquired and then displayed in tabular form or as dots on a state map display. In tabular form, the digital words may be displayed in various selectable groups; the data word used as a trigger word of the group is displayed in a brightened state. When using the map display format, each digital word is displayed as a dot. One half of the word is utilized to determine the X-axis position and the other half of the word is utilized to determine the Y-axis position. The sequence of the digital words thus displayed is shown by a vector drawn between the dots. A cursor is provided to allow selection of a map area to be displayed on an expanded scale. The display also indicates the relative occurrence of a particular digital word. The more often a state repeats, the brighter its dot. Once familiar with the patterns generated by a particular sequence of words, the user can recognize whether or not a particular pattern is correct without having to do a state-by-state study of a tabular listing.

Inventors

• 👤 Justin S. Morrill, Jr.
• 👤 William A. Farnbach
• 👤 Charles T. Small

Bibliographic Details