US4039972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Crystal controlled logic gate clock pulse generator
Assignee: Digital Equipment Corp
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Filing: 1976-01-19
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Granted: 1977-08-02
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Expires: 1996-01-19
Abstract
Abstract A self-triggered clock pulse generator for high frequencies comprising an oscillating quartz crystal which is included in a loop together with a capacitor and a single, non-inverting gate. An averaging feedback is obtained by means of an inverting gate and an integrating circuit, which are connected in series between the output of the non-inverting gate and the input of the gate which is connected to the crystal.
Inventors
- 👤 Rudy Dirk Anthonie Scholten
- 👤 Antonius Gerardus Visser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:32
CPC Classifications
H; H03; H03L; H03L1/00; H03B; H03B5/00; H03B5/30; H03B5/32; H03B5/36; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/26; H03K3/28; H03K3/281; H03K3/282
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
81 words
A device for the self-triggered generation of a series of cyclically recurring clock pulses, comprising a non-inverting logic gate, a piezoelectric oscillator element having one lead connected to an input and the other lead coupled to the output of the non-inverting gate, and a feedback loop connected between the output and the input of said non-inverting gate, said loop including a series combination of an inverting gate, an integrating network and means for setting the switching voltage of said non-inverting gate.
Claim 2
Independent Claim
81 words
A device for the self-triggered generation of a series of cyclically recurring clock pulses, comprising a non-inverting logic gate, a piezoelectric oscillator element having one lead connected to an input and the other lead coupled to the output of the non-inverting gate, and a feedback loop connected between the output and the input of said non-inverting gate, said loop including a series combination of an inverting gate, an integrating network and means for setting the switching voltage of said non-inverting gate.
Claim 3
Dependent Claim
24 words
A device as claimed in claim 1, wherein said other lead of said oscillator element is coupled to said non-inverting gate by a capacitor.
Claim 4
Dependent Claim
16 words
A device as claimed in claim 1, wherein said non-inverting logic gate is Schottky TTL gate.
Claim 5
Dependent Claim
16 words
A device as claimed in claim 1, wherein the said non-inverting gate is an ECL gate.
Claim 6
Dependent Claim
36 words
A device as claimed in claim 4, wherein said non-inverting gate and said inverting gate are constituted by means of a single ECL gate having its inverted output connected to an input of said integrating network.
Claim 7
Dependent Claim
42 words
A device as claimed in claim 1, wherein said inverting gate has at least one additional control input to block the said series combination by a first signal and to unblock the same by a second signal appearing on said control input.
Claim 8
Dependent Claim
28 words
A device as claimed in claim 1, further comprising an inverting delay line and a further inverting gate connected in series to the output of said non-inverting gate.
References Cited (Backward Citations)
US3829790A
Cited
US3911378A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-01 | 1981-01-31 | 1981-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-01 | 1985-01-31 | 1985-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-01 | 1989-01-31 | 1989-08-02 | $7700.00 | Window Closed / Lapsed |