Pulse code modulation compressor

Claim 1

A pulse code modulation compressor for companding pulse code modulation signals having a sign bit, comprising: A. a magnitude comparator for comparing pulse code modulation signals having first and second inputs and decision outputs; B. a first shift register connected to said first comparator input and having an input; C. a memory having an address input and a pulse code modulation output programmed to convert compressed pulse code modulation signals to linear pulse code modulation signals, said memory output connected to said second comparator input; D. a second shift register having a single stage set of bit cells equal in number to the number of bits in a compressed pulse code modulation word and a sign bit cell to be processed, said word bit cells connected to said comparator decision outputs; E. a logic circuit connected between said magnitude comparator and said second shift register comprising; 1. a first NAND gate having one input terminal connected to the sign bit at said magnitude comparator first input and another input connected to one said magnitude comparator decision output; 2. a second NAND gate connected through an inverter to said sign bit at said magnitude comparator first input and having another input connected to another of said magnitude comparator decision outputs; 3. a third NAND gate having an input connected to said first NAND gate and a second input connected to said second NAND gate and having an output connected to each bit cell of said address register except the most significant bit cell through a second inverter; and F. clock means connected to said second register to provide a series of successively more accurate memory address pulse code modulation words in said second register.